Intel mcs-48 manual MIN MAX Unit

8251A/S2657

Other Timings:
SYMBOL	PARAMETER
tCY	Clock Period
tq,	Clock High Pulse Width
1:$	Clock Low Pulse Width
tR, tF	Clock Rise and Fall Time
tDTx	TxD Delay from Falling Edge of TxC
fTx	Transmitter Input Clock Frequency
	lx Baud Rate
	16x Baud Rate
	64x Baud Rate
tTPW	Transmitter Input Clock Pulse Width
	1x Baud Rate
	16x and64x Baud Rate
tTPD	Transmitter Input Clock Pulse Delay
	1x Baud Rate
	16x and 64x Baud Rate
fRx	Receiver Input Clock Frequency
	lx Baud Rate
	16x Baud Rate
	64x Baud Rate
tRPW	Receiver Input Clock Pulse Width
	lx Baud Rate
	16x and 64x Baud Rate
tRPD	Receiver Input Clock Pulse Delay
	lx Baud Rate
	l6x and 64x Baud Rate
tTxRDY	TxRDY Pin Delay from Center of last Bit
tTxRDY CLEAR	TxRDY ~ from Leading Edge of WR
tRxRDY	RxRDY Pin Delay from Center of last Bit
tRxRDY CLEAR	RxRDY ~ from Leading Edge of RD
tiS	Internal SYNDET Delay from Rising
	Edge of RxC
tES	External SYNDET Set· Up Time Before
	Falling Edge of RxC
tTxEMPTY	TxEMPTY Delay from Center of Last Bit
twc	Control Delay from Rising Edge of
	WRITE (TxEn,DTR, RTS)
tCR	Control to READ Set-Up Time (DSR, CTS)

MIN.	MAX.	UNIT
320	1350	ns
140	tCY-90	(IS
90		ns
	20	ns
	1	J.Ls
DC	64	kHz
DC	310	kHz
DC	615	kHz
12		tCY
1		tCY
15		tCY
3		tCY
DC	64	kHz
DC	310	kHz
DC	615	kHz
12		tCY
1		tCY
15		tCY
3		tCY
	8	tCY
	6	tCY
	24	tCY
	6	tCY
	24	tCY
16		tCY
20		tCY
8		tCY
20		tCY

TEST CONDITIONS

Notes 5, 6

Note 7

Note 7

Note 7

Note 7

Note 7

Note 7

Note 7

Note 7

Note 7

5.The TxC and RxC frequencies have the following limitations with respect to elK.

For 1x Baud Rate, fTx or fRx < 11(30 tCY)

For 16x and 64x Baud Rate. fTx or fRx < 1/(4.5 tCyl

6.Reset Pulse Width ~ 6 tCY minimum; System Clock must be running during Reset.

7.Status update can have a maximum delay of 28 clock periods from the event affecting the status.

9-5 00216A