Manuals / Intel / Personal Care / Microscope & Magnifier

Intel mcs-48 manual 8205

Models: mcs-48

1 478

Download 478 pages 26.88 Kb

Page 279

8205

HIGH SPEED 1 OUT OF8 BINARY DECODER

•1/0 Port or Memory Selector

•Simple Expansion - Enable Inputs

•Hig"h Speed Schottky Bipolar Technology - 18 ns Max Delay

•Directly Compatible with TTL Logic Circuits

•Low Input Load. Current - 0.25 mA Max, 1/6 Standard TTL Input Load

•Minimum Line Reflection - Low Voltage Diode Input Clamp

•Outputs Sink 10 mA Min

•16·PinDualln·LineCeramic or Plastic Package

The Intel'"8205 decoder can be used for expansion of systems which utilize input ports, output ports, and memory components with active low chip select input. When the 8205 is enabled, one of its 8 outputs goes "low", thus a single row of a memory system is selected. The 3·chipenable inputs on the 8205 allow easy system expansion. For very large systems, 8205 decoders can be cascaded such that each decoder can drive 8 other decoders for arbitrary memory expansions.

The 8205 is packaged in a standard 16-pin dual in-line package, and its performance is specified over the temperature range of oDe to +75°e, ambient. The use of Schottky barrierdlode clamped transistors to obtain fast switching speeds results in higher performance than equivalent devices made with a gold diffussion process.

PIN CONFIGURATION

Ao		16	V.cc
A,		15	0 0
A2	3	14	0,
E,	4	13	°2
		8205
E2	5	12	0 3
E3	6	11	0.
0,		10	°5
GRD	8		0 6

PIN NAMES

AO· A2 ADDRESS INPUTS

E ,. E3 ENABLE INPUTS 00· 0, DECODED OUTPUTS

LOGIC SYMBOL

Ao

A,

A2

8205

E,

E2

EJ

ADDRESS

ENABLE

OUTPUTS

Ao

A,

A,

E,

E,

E3

0 1

2

3

•

0

6

)

L L L L L H L H H H H H H

H

H L

L

L

L

H H L

H H H H H

H

L

Ii L

L

L

H H H

L

H H H H H

H

H

L

L

L

H H H H L

H

H H

H

L

L

H L

L

H H H H H L

H H

H

H L

H L

L

H H H H H H L

H

H

l

H H

L

L

H H H H H H H L

H

H H H L L

H H H H H H H H

L

X X X L L

L

H H H H H H H

H

X X X

H L

L

H H H H H H H

H

X X X

L H

L

H H H H H H H

H

X X X

H H

L

H H H H H H H

H

X X X H L H H H H H H H H H

X X X

L H H H H H H H H H H

X X X

H H H H H H H H H H H

8-18	AFN-00204B-ol

Image 279

Intel mcs-48 manual 8205

Contents

Page September MCS-48 Family of Single Chip Microcomputers UsersmanualPrompt BXPMultibus CreditTable of Contents 8051/8751/8031 Microcomputer ChaptersPacking Information Emulation BoardEmulation Board 10-19 UPP-103 Universal Prom Programmer Insite UsersLibraryPage Ntroduction Page Introduction to MCS-48 Introduction 5.0 and 10.0 J,Lsec Cycle Versions8021 is code compatible but not pin compatible with Introduction TilEprom Introduction Accumulator Function of a ComputerTypical Computer System Architecture of a CPUProgram Counter Jumps, Subroutines and the Stack Arithmetic/Logic Unit ALU Three levels of subroutines may be ac- commodatedInstruction Register and Decoder Address RegistersInstruction Fetch Control CircuitryComputer Operations TimingMemory Write Input/OutputInterrupts To the next instructions When finished the processor continues onMOV R2, #05 Step No. Hex Code Assembly Code MOV RO, #32Our machine language program then becomes Step Hex CodeADD A, # ALFA*BETA/2 Cpla ADD A, REGSUB R7 Function Definition Hardware ConfigurationDeveloping An MCS-48 Based Product EducationPrompt Production Intellec Development SystemPage Single Component MCS-4S S~stem Page Summary ArchitectureArithmetic Section ~BUS Location Single Component SystemInput/Output Single Component SystemSingle Component System Pointer R23+--1 R Jump ConditionsInterrupt Timing Oscillator As a TimerAs an Event Counter Clock and Timing CircuitsALE --f---+--+ Instruction 111LOVI Power Down Mode BUS PCO·7RUN Stop Pin Description Number Function 00-07Designation ProgProgramming, Verifying and Erasing Eprom ResetSingle Component System Disabling Internal Program Memory ResetTest and Debug Single StepReading Internal Program Memory Following is a functional description of the major elements Program MemoryOscillator and Clock Timer/Event CounterQUASI-BIDIRECTIONAL Port Structure Input/Output Capabilities1 T1 Input High Current OutputsExpanded I/O Jump Test Condition Instructions Accumulator ResetCarry Flag Timer Overflow Flag 10 CPUFunctional Specifications Program MemoryData Memory See the 8021 description, .8, for a com- plete explanation 15Timer/Event CounterOscillator and Clock Port 0 Comparator InputsHigh Current Outputs Expanded 1/0Test and Interrupt Inputs 1-3 VAC Analog to Digital Converter Ill19 CPU Expanded Page Expansion of Program Memory SummaryInterrupt Routines Expanded MCS-48 SystemAI? Latch ROMLatch IOW Expansion of Data MemoryEXPAND!!D MCS-48 System Expansion of Input/OutputRead OO-Port #4 Write Port #5 10 or Port #6 Port #7 II AARD Display KeyboardExpansion Examples See Also Chapter Expanded MCS-48 SystemMulti-Chip MCS-48 Systems =====ll 8~~5 Memory Bank SwitchingPort 2 Operations Control Signal SummaryPort Characteristics BUS Port Operations000 Page Page Instruction SET Instruction SET Subroutines Instruction SET Instruction SET Summary 8021 RET Instruction SET SummarySymbols and Abbreviations Used DBFPSW ADD A,#data Add Immediate Data to Accumulator ADD A,R r Add Register Contents to AccumulatorADD A,@R r Add Data Memory Contents to Accumulator Addc A,R r Add Carry and Register Contents to AccumulatorAddc A,#data Add Carry and Immediate Data to Accumulator ANL A,R r Logical and Accumulator With Register MaskANL A,@R r Logical and Accumulator With Memory Mask ANL A,#3+X/Y Andacc Contents with Value of EXP 3+X/Y ANL A,#data Logical and Accumulator With Immediate MaskAnld Pp,A Logical and Port 4-7 With Accumulator Mask INC RO Increment REG RET Return to Main Program Andport 4 ContentsWith ACC Bits MOV RO,#50 Move 50DEC to Address11 00 0 Flag 0 is cleared to zero 10010101111 Contents of the accumulator are cleared to zeroCpla CPL Aacc Contents are COMPLE- Mented to 11010 Flag 1 is cleared to zero F1-0Overflow to C DA Aacc Adjusted to 00000001 with C SETAC 7 4 3 0 o 1 0 ADD SIX to Bits 010100001 ADD SIX to BitsDEC Rr Decrement Register Not in 8021 Example Decrement contents of external data memory locationA,Pp Input Port or Data to Accumulator EN I Enable External InterruptEN Tcnti Enable Timer/Counter Interrupt Not Ento ClK Enable Clock Output Not in 8021,8022INC a Increment Accumulator INC Rr Increment RegisterINC @R r Increment Data Memory Location JC address Jump If Carry Is Set IputoPort 0 Data to Accumulator 8021, 8022 OnlyINS A,BUS Strobed Iput of BUS Data to Accumulator JBb address Jump If Accumulator Bit is Set Not in 8021JNC address Jump If Carry Is Not Set JF1 address Jump If Flag 1 Is Set Not in 8021JMP address Direct Jump Within 2K Block Jmpp @A Indirect Jump WithinJNZ address Jump If Accumulator Is Not Zero JNI address Jump If Interrupt Input is Low Not in 8021Jnto address Jump If Test 0 Is Low Not JNT1 address Jump If Test 1 Is LowJump to Countroutine Jump to TimerroutineIFTF=1 Jump to Location 53 DECMev A, #data Move Immediate Data to Accumulator MaV A,PSW Move PSW Contents to Accumulator Not in 8021MaV A,R r Move Register Contents to Accumulator MaV A,@R r Move Data Memory Contents to AccumulatorMev A,T Move Timer/Counter Contents to Accumulator MaV @Rr,A Move Accumulator Contents to Data Memory Movo A,Pp Move Port 4-7 Data to Accumulator Movo Pp,A Move Accumulator Data to PortMovp A,@A Move Current Page Data to Accumulator Current page are Moved to ACC Maxdm Movx A,@R1 Move Contents of LocationMOVP3 A,@A Move Page 3 Data to Accumulator Not in 8021,8022 Not in 8021ORL A,#data Logical OFJ Accumulator With Immediate Mask NOP The NOP InstructionORL A,Rr Logical or Accumulator With Register Mask ORL A,@Rr Logical or Accumulator With Memory Mask8021 Outl Pp,A Output Accumulator Data to Port 1 or Retr Return With PSW Restore Not in 8021 Contains Rrnc RR Anew ACC Contents areExample Assume carry is not set and accumulator contains Rrtc RRC a Carry is SET and ACC48 HEX SEL MBO Select Memory BankJMP $+20 Jump to LocationBIT 3 is SET REG 7=8 Stop Tcnt Stop Timer/Event-Counter10110101011 Jump to Routine Intif ACeStrt T Start Timer Strt CNT Start Event CounterSwap a Swap Nibbles Within Accumulator XCH A,R r Exchange Accumulator-Register Contents XCH A,@R r Exchange Accumulator and Data Memory ContentsXchd A,@R r Exchange Accumulator and Data Memory 4-Bit Data XRL A,#data Logical XOR Accumulator With Immediate Mask XRL A,@R1 Xoracc Contents with Mask LocationXRL A,Rr Logical XOR Accumulator With Register Mask XRL A,@Rr Logical XOR Accumulator With Memory MaskAppli~ation Examples Page Driving from External Source Crystal Oscillator ModeLC Oscillator Mode IntroductionApplication Examples Reset~~J Rvv-i T1 Multiple Interrupt Sources Ii6 Tf ~rServes as address latch Tt-2 A717&A3 ROM XtaliBoth 1/0 and RAM are addressed as data memory =!-39TOThis configuration is explained in section ResetF1L Expander Pinnumbers are Different for ~fd...LDB6 r ~1~Adding 8 Input Lines ·15 Application ExamplesAdding Output for KEYBOARD/DISPLAY Scanning RT T T T T JfLSubstitute a Application Examples Emulator Circuit DESCRIPTION-6 MHZInterface to Drum Printer Timer RAMII Keyboard Display Microwave Oven Controller Double Store Double ADDDouble Subtract Double LoadDouble Right Arithmetic Shift Application Examples Double ExchangeDouble Left Logical Shift Double Right Logical ShiftInterrupt Handling Application Examples Binary Multiply2sCOMPLEMENT and ADD Application Examples Byte Processing SystemR1,A CPL Subtract Second from First INCSee AP-49 8 MULTIPLY-ASSEMBLED by MCS-48 Macro AssemblerIIn ·1 16 x 8 DIVIDE-ASSEMBLED by MCS-48 Macro ASS.E.MBLERSEE AP-49 APP\,JCATION Examples16 x 8 DIVIDE-ASSEMBLED by MCS-48 Macro Assembler see AP-49 Page MCS-4STMComponent Page IIH!T Hmos Single Component 8-BIT MicrocomputerProgram store enable. This Used to enable data ontoAddress latch enable. This Signal occurs once duringS04SH/S04SH-1 /S035HL-1/S035H L-1 Absolute Maximum RATINGS· Inter 8048H/8048H-1/8035HL/8035HL.1BUS Timing AS a Function of TCY Port 2 Timing8035HL S04SH/S04SH-1/S035HL/S035HL-1Waveforms Read From External Data MemoryJ3 Xtal Z 8048H/8048H·1/8035HL/8035HL·1Rll PIN Configuration Logic Symbol Block DiagramBlock Diagram PIN Configuration Logic SymbolPIN Description 8048/8035L/8748/8748-6/8748-8/8035/8035-8AFN-Q1354A-03 Output Low Voltage 10L = 1.8 mA All Except XTAL1, XTAL2, ResetInput High Voltage X1, X2, RESEi VOL =2.0 mA===i---h·1 Characteristics Port 2 Timing PROGRAMMING, VERIFYING, and Erasing the 8748 Eprom Crystal Oscillator ModeLC Oscillator Mode Driving from External SourceTA = 2SOC ± SoC, Vee =SV ± S%, Voo = 2SV ± Waveforms for Programming Verify .I.~---PROGRAMPROMPT-48 Microcomputer Design Aid, or Intel Corporation 108048/8748/8035L 108048/8748/8035L BUSP1, P2BUS, P1, P2 Operating CharacteristicsIDS0481S7481S035L Absolute Maximum RATINGS·PSEN, RD to Data TAW Address Setup to WR260 TAD Address Setup to Data TOR Data HoldTA= -40·Cto +85·C, Vcc=5V ±10%, Vss=OV CharacteristicsTop Port Control Setup Before Failing Edge of Prog TpL Port 2 I/O Data SetupProg Crystal Oscillator Mode Driving from External SourceReset +-----t XTALlTA = 25C ± 5C, Vee = 5V ± 5%, Vee = 25V ± TA =25C ± 5C, Vee =5V ± 5%, Vee =25V ±PROMPT-48 Microcomputer Design Aid. or Waveforms for ProgrammingInter Lcoscillator Mode VooProgramming Verification EA Program or Verify Voltage High Level 21.5 24.5 8748 IPHUnit Test Conditions Voo Program Voltage High Level 24.0 2S.0M8048/M8748/M8035L EA 5M8048/M8748/M8035L Prog Pin #TLP Port 2 1/0 Data Hold 120 Tcp Port Control Setup Before FallingTpL Port 2 1/0 Data Setup Tpo Output Data Hold Time Tpp Prog Pulae WidthALE JI ~----r---I L CharacteristicsBUS, P1, P2 AN D Operati NG CharacteristicsInter 80411803118031 8049/8039 Symbol Parameter Min Max Unit Operating CharacteristicsALE JIL --------..1.--1----L Mask Programmable ROM External ROM or Eprom MHz Operation 18049/8039INr Til IntJ18049/8039BUS, RD, WR, PSEN, ALE VOH1 VIH1BUS, RD, WR, PSEN, ALE VOL2Waveforms TAFC--1 I~OATING-I t=t orUnit Conditions Note Output Data Setup Time 230Port 2 1/0 Data Setup 300 TA = -400C to +850 C, Vee = Voo = +5V ±10%, Vss = OVXT AL1 Crystal Oscillator Mode LC Oscillator Mode8021 PIN Configuration Logic Symbol Block DiagramT1, RESEl OC to 70CV1Hl Input High Voltage Xtal 1 & 2, T1 VIH10% Input high voltage all except Xtal 1XTAL2 ALE8022 Varef ANO,AN1 ALE Xtal Reset AvssProg POO-P07 VTHFzx 8022Port 2 Timing IpAL---ooj·1Analog Input Timing AID Converter CharacteristicsAnalog Input 0, Analog Input Timer Mnemonic for in-page OperationCNT Inter GND PIN DescriptionAbsolute Maximum Ratings ~~x 125 P20-P23 -- .....--X..... ...Jr 14P52 108243GND 1824318243 Tes 1 2 3 4 5 6 7 8 9 10 11 12 # pins= 60 mA-+- 8 mA/pin = 7.5=Output Expander Timing 16,384·8IT ROM with Ready ResetCE1 CE2ILO Symbol Parameter MIN MAX8355/8355-2 IIICl ~ +- Al ~Input Mode Output Mode8355/8355·2 Directly Compatible with SOS5A CPU PIN Configuration Block Diagram8755A 8755AFUNCTIONAL PIN DefinitionPROG/CE1 UPP UP2121 SA Programming Module Cross Reference Module Name USE withUPP UPPI41Ready Hold Time Symbol Parameter MIN MAX VIL8755A CommentProm Read, 1/0 Read and Write Timing Clock Specification for 8755AWait State Timing Ready =0 Specification Programming ITA =OC to 70C Vee =5V ± 5% Vss =OVVoo Programming Voltage during Write To Eprom Program Mode Timing Diagram 8156-2 Enable8085A 8085A-2 8155-2Timer OUT 8155/8156/8155-2/8156-28155/8156 PIN Functions 8156 Internal Registers DescriptionReading the Status Register Programming Command RegisterSTB Control Input Mode Output ModeINPUT/OUTPUT Section BFLowLow INTRLowHighPca 8155/8156/8155-2/8156-2Timer Section Example Program 8085A Minimum System Configuration Interval Timer Interrupt LevelsWR AD ALE Symbol Parameter MIN MAX Units Test Conditions VIL MIN MAX Units Symbol ParameterWrite Cycle Read CycleWI\ J / j 8155/8156/8155-2/8156-2Basic Output Mode Basic Input ModePIN Names PIN Configuration Block DiagramTruth Table for Control and Data BUS PIN Status Truth Table for Power Down and Function Enable8185/8185-2 Operational DescriptionComment Absolute Maximum Ratings8185/8185-2 Page Page SINGLE-COMPONENT 8-BIT Microcomputer 8051 CPU Architecture 0INTRODUCTION8051 Family MACRO-VIEW of the 8051 ArchitectureON-CHIP Peripheral Functions 1Interrupt System21/0 Facilities 8031/8051/8751 8031/8051/8751 3Timer/Event Counters4Serial Communications 8031/8051/8751~=- J~~====~ ~DATA Circuit ground potential 8031/8051/8751Family Development System and Software Support PsenXTAL1 XTAL2Insite Library Symbol Parameter Min Typ Max UnitsUniversal Prom Programmer Personality Card UPP-851 Workshop12MHz Clock Data Memory Write Cycle 8051 Instruction SET Summary Inter8031/8051/8751All mnemonics copyrlghted@ Intel Corporation InterPage Compatible MCS-48 Components 1024 X 4 BIT Static RAM PIN Configuration2114A Family Symbol Parameter Address -..II-------------i--lUnit Normauzed Access Time VS Supply Voltage Typical D.C. and .A.C. Characteristics2316E 16K 2K 8 ROM 2316E Data ----=HIGHZ~--~~~~~~~~~~-OU-T~TV-ALIO~~~JlJJI PIN Connection During Read or Program PIN ConfigurationNco and A.C.OPERATING Conditions During Read BB Power Supply 5V±5% 5Vt.5% -5V±5% -5V±10%Operating Characteristics FamilyVIN = OV Address to Output Delay2708·1 limits 2708·6Limits Units Input CapacitanceWaveforms FamilyPIN Names PIN Configuration Mode SelectionCE = VIH. OE = VIL ProgrammingCout 2716Typical 16K Eprom System 2716Device Operation 2716Industry Standard Pinout . .. Jedec Approved8086·2 MPU .. .Zero Wait State Two Line Control8205 Ei==~ fEH2·E3 Eii-+-IH-+t-t r A13 --..,-H+-q E8205 ApplicationsState Decoder Circuit MIN MAX Typical Characteristics\.. ~ ~ TA = O·Cto + 75·C, Vee = 5V ± 5%Test Waveforms Switching CharacteristicsCharactristics Conditions of Test Test LoadDB ---------- -- +i PIN Configuration Logic DiagramIT os GD ~s ------- + HIE D Functional DescriptionIl D +-+1DS2 , ------,----.J Basic Schematic SymbolsII. Gated Butter 3-State Gated Buffer8212 VI. Output Port With Hand-Shaking Here the 8212 is used as the status latch for an 8080ACLR AD2Bossa AD4 AD5 AD6 AD7 ~DI, Stbdo LOW OrderIOL = 15mA 8212Output Currents 100mA Input Load Current, ACK, OS2, CR VF = A5VIli FfiDOs Output Capacitance 8pF Switching CharacteristicsTyp. Max CIN 051 MD Input Capacitance 9pF 12pF 052. CK. ACK. DI1-Dls Input Capacitance 5pFTCI SGS II,DIcex 821413214Capacitances 8214/3214Test Conditions Test Load Circuit Inte001 ·BITPARALLEL Bidirectional BUS DriverControl aatlng OlEN, CS Bidirectional DriverOUT O---T Waveforms CharacteristicsVoli VOL2 IFI IF2 IRI IR2 VIL VIHApplications of the 8216/8226 821618226VCC 8282/8283Octal Latch 010PinD.scrlptlon PIN Definitions Operational DescriptionTehoz VOL VOHTivov TshovJJ\~ J/~~ 8282/8283 Vee IntelBo- B7 Ao-A7Characteristics for 8286/8287 Jk~ Output Delay vs. CapacitanceOutput Page Page Synchronous 5·8 Bit Characters Synchronous and Asynchronous OperationFeatures and Enhancements Capacitance Capacitance pFIofl Input Waveforms for AC Tests Bus Parameters !NoteMIN MAX Unit Programmable Interval Timer VIIi -.,--.,q GeneralControl Word Register System InterfaceControl Word Format Operational DescriptionGeneral Programming825318253·5 =41 I---t--n --+ Mode 2 Rate Generator8253/8253-5 LSBMSB Reading While Counting Read Operation ChartMode Register for Latching Count Read OperationsOe to 700 e Write Timing Bus Parameters NoteInput Waveforms for A.C. Tests Re.dCycleClock and Gate Timing 825318253·5Programmable Peripheral Interface PIN Configuration 8255A Block DiagramFace peripheral devices or structures 8255A18255A·58255A Functional Description 8255A Basic OperationPorts A, B, and C PIN Configuration PIN Names8255A18255A·5 Group a and Group B ControlsMode Selection Single Bit Set/Reset Feature8255A Operational Description Interrupt Control Functions Operating ModesMode 0 Configurations Mode 0 Port DefinitionPA7·pAo 8255AJ8255A·5II I I I, I0 I0 I0 Intr Interrupt Request Input Control Signal DefinitionTPH IBF Input Buffer Full F/FInte B Output Control Signal Definition10 I ·IOMXlXl InteaInput Operations Combinations of ModeBidirectional Bus 1/0 Control Signal Definition Output OperationsLtAOi 8255.Al8255A·5\, I, erXtJ I0\ ErXtJ I 0\Mode Definition Summary 30AFN-00744A-14Only Printer Interface Applications of the 8255AMSB PC, rCapacitance MIN. MAX Unit ReadCIR TRIT LtR1Bj TwBSIB-Ii SP/EN Programmable Interrupt Controller8259A Interrupts in Microcomputer Systems8259A Basic Functional Description INT Interrupt Interrupt Request Register IRR and IN·SERVICE Register ISRPriority Resolver Interrupt Mask Register IMRInterrupt Sequence 8259A8259A Interface to Standard System Bus Cascade BUFFER/COMPARATOR~O ~ ~ Input Operation Read Disable FunctionProgramming the 8259A GeneralInitialization Command Word 3 ICW3 Initialization Command Words 1 and 2 ICW1,ICW28259A 0 I 0 I 0 I 0 I 0 lID, liD, lIDoOcwa Operation Command Words OCWsOperation Control Word 1 OCW1 Operation Control Word 2 OCW2 Operation Control Words OcwiOperation Command Word Format OJNTlR,-r-- I-i-Ioo r,-r,-r Special Fully Nested Mode Special Mask ModeBuffered Mode Fully Nested ModeWol Word enabled onto the data bus during m5 isAutomatic END of Interrupt Aeoi Mode Rotating Priority Mode B Rotation by SoftwareOH-++-+ Priority Cell Simplified Logic DiagramLevel Triggered Mode This mode is programmed using bit 3 in ICW18272 Description Features8272 Registers CPU Interface8272 Reset to the Interrupt signal Polling FeatureIntJ Command SET Read Data Command DescriptionsTransfer Capacity EN End of Cylinder Flag No No Data Flag Write DataReadid Write Deleted DataRead Deleted Data Read a TrackScan Commands Sense Drive Status RecalibrateSense Interrupt Status SpecifyUsa Status Registers BIT Name Symbol DescriptionVIN=OV DC CharacteristicsVIL CLK & WR CLK VIH CINI»ICY ~-----~---V Timing Measurement Conditions Sel-IBlock Oiagram LI3Brief Description of HDLC/SDLC Protocols 8273, 8273·4, 8273·8Flag DET 32XCLiRAM Programmable KEYBOARD/DISPLAY Interface827918279-5 Hardware DescriptionPrinciples of Operation 827918279·5 Software Operation Data Write End Interrupt/Error Mode SetStatus Word Data ReadScanned Keyboard Mode, 2·Key Lockout Interface Considerations===~ Applications General Block DiagramSymbol Test TYP MAX VIL2IIL1 BUS Parameters Input Waveforms for A.C. Tests8279 Display Waveforms Scan Timing Scan WaveformsGpib TALKER/LISTENER 8291 General Description System Diagram8291 General Purpose Interface BUS GpibPpas AcdsPacs AcrsDAC SH,AH,T,TE,L,LE,SR,RL,PP,CAH,C Remote Messages Received ATN SH,AH,T,TE,L,LE,PP,C DABEND Remote Messages Sent ATN DABDAC DAVDontCare All Write RegistersInterrupt Registers SPAS---SPAS Spasc Llcno LLO LlocMenting this feature, with 80 and Bi enabied from ITO ILO I 0 I 0 I 0 I 0 Admi Aomoi Command Pass Through Register Provided forSection on Parallel Poll Protocol Auxiliary Commands Auxiliary Mode RegisterAuxiliary Register B Internal Counter2NF Auxiliary Register aParallel Poll Protocol Reset Procedure8291 Using DMA 8291 to 8291A Software Compatibility Iloh Device Electrical CharacteristicsVOH-INT IlolTiming Waveforms TwA~Gpib Timingsii Figure A.1 State Diagrams next Modified State Diagrams101 Settling Time for Multiline Messages 21st Response to ATN 200ns Interface Message Accept Time tTE,L,LE,C,CE Appendix C Figure C-l -Wire Handshake Timing atFigure C.2. Handshake Flowchart 105 IIIL---,--11 ,--I106 Gpib ControllerAi1W Gpib Transceiver OATA1 EOIBUS1 BUS9NDAC* I/O Mode 0 PIN Description=OV GpibNrfo TILIeee Gpib Mode 1 PIN Description Mode 2 PIN DescriptionNdac Ieee NrfdMode 3 PIN Description LIEN R1LTiR1 Capacitance Operating Characteristics8293 Absolute Maximum Ratings·118 CharacteristicsTA = O·Cto 70·C Vee= 5.0V ± 10% GND = OV TYP.· MAXOutput Loading Test Circuits Waveforms 82938294 ·122 8295123 ====JUPI·41A Features Enhancements Signal Description Mnemonic Description Bytes CyclesData Moves 8041 Al8641 Al8741 a IU1 VIUWrite OPERATION-DATA BUS Buffer Register Input and Output Waveforms for A.C. TestsTypical 8041/8741A Current Read OPERATION-DATA BUS Buffer RegisterCHARACTERISTICS-PORT CHARACTERISTICS-DMAWAVEFORMS-DMA VOO PROGRAMMING, VERIFYING, and Erasing the 8741A EpromTiming Specification for Programming Specification for ProgrammingVdol 8041Al8641 Al8741A ProgramSupport Products Page Credit Microcomputer Development System10-2 MODEL225 Functional DescriptionControl InterMODEL225 System ComponentsIntegral CRT Peripheral InterfaceSpecifications 9800292 Notavailable on bus110V, 60 Hz 5.9 Amp 220V, 50 Hz 3.0 Amp 9800556Page Intellec Prompt MCS·48 Microcomputer Design AID Single Component Compu.ter Intellec Prompt FeaturesIntellec Prompt Prompt 48 Commands and FunctionsMCS-48 Processors Intellec Prompt Functional DescriptionUser Interrupt causes an Interrupt only If Prompt system Is running a user programCycle Time tCY = 2.5,..s Clock 6 MHz ± 0.1% Ordering Information MCS·48 IN·CIRCUIT Emulator ICE·49 ~ L ·GO from .START Till XDATA. Rslt Written Memory MappingISIS·II ICE·49EM1 Emulation Board EM1 MDS·EM1 EM1 SpecificationsDC Power Vcc5V ±5% Icc 300 mA max Ordering InformationEM2 Emulation Board AN1 40·PIN Socket Configuration EM2 Block DiagramEM2 ANOEM2 UPP-1P3MDS-EM2 September Canadian Sales OfficesTAvnet Electronics McCormick Avenue Costa Mesa Canadian DistributorsIntJ International DISTRIBUTORS/REPRESENTATIVES Bowers Avenue International Sales and Marketing OfficesINTEL$ Marketing Offices International Sales and Marketing OfficesCanadian Service Offices