Intel mcs-48 manual EN I Enable External Interrupt, EN Tcnti Enable Timer/Counter Interrupt Not

INSTRUCTION SET

Note: A 12-bit address specification does not cause an error if the DJNZ instruction and the jump target are on the same page. If the DJNZ instruction begins in location 255 of a page, it must jump to a target address on the following page.

Example: Increment values in data memory locations 50-54.

MOV RO,#50	;MOVE '50'DEC TO ADDRESS
	;REG 0
MOV R3,#5	;MOVE '5'DEC TO COUNTER
	;REG 3
INCRT: INC @RO	;INCREMENT CONTENTS OF
	;lOCATION ADDRESSED BY
	;REG 0
INC RO	;INCREMENT ADDRESS IN REG 0
DJNZ R3, INCRT ;DECREMENT REG 3 - JUMP TO
	;'INCRT'IF REG 3 NONZERO
NEXT -	;'NEXT'ROUTINE EXECUTED
	;IF R3 IS ZERO
EN I Enable External Interrupt	(Not in 8021)

10000101011

External interrupts are enabled. A low signal on the interrupt input pin initiates the interrupt sequence.

EN TCNTI Enable Timer/Counter Interrupt (Not in 8021)

10010101011

Timer/counter interrupts are enabled. An overflow of the timer/counter initiates the interrupt sequence.

ENTO ClK Enable Clock Output (Not in 8021,8022)

10111101011

The test 0 pin is enabled to act as the clock output.

This function is disabled by a system reset.

Example: EMTSTO: ENTO ClK ;ENABlE TO AS CLOCK OUTPUT

IN A,Pp Input Port or Data to Accumulator

10000110ppi

This is a 2-cycle instruction. Data present on port 'p' is transferred (read) to the accumulator. In the 8021 IN A,P2 inputs P20-P23 to AO-A3 while A4-A7 is set

to zero.

(A).-. (Pp)p=1-2

Mnemonics copyright Intel Corporation 1976.

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