Intel mcs-48 manual Power Down Mode, BUS PCO·7, RUN Stop

		SINGLE COMPONENT SYSTEM
		SINGLE STEP CIRCUIT
		+6V
	+BV	SINGLE 10K
		STEP
MOMENTARY	10K	r,UN
PUSHBUTTON

'---:P=RE~SE=T-- ,

+6V Do

+BV

,------1> CLOCK

10K

DEBOUNCE

LATCH

' ---- <1ALE-

1/27400

ALE

ss

SINGLE STEP TIMING

,

I S3 84 I S5S1 I S2 S3 S4 S5 I

-.JI

BUS		<	PCO·7	)
P20·23	1/0	X PC8·11		X
	RUN		STOP

1/0

RUN I STOP

2.1.14 Power Down Mode

(8048, 8049, 8039,8035L)

Extra circuitry has been added to the 8048 ROM version. to allow Rower to be removed from aU but the 64/128 x 8 data RAM array for low power standby operation. In the power down mode the contents of data RAM can be maintained while drawing typically 10% to 15% of normal operating power requirements.

Vee serves as the 5V supply pin for the bulk of 8048 circuitry while the Voo pin supplies only the RAM array. Ih normal operation both pins are at 5V while in standby Vee is at ground and only Vob is maintained at 5V. Applying Reset to the processor through the RESET pin inhibits any access to the RAM by the processor and guarantees that RAM cannot be inadvertently altered as power is removed from Vee.

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