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Intel mcs-48 manual AFN-Q1354A-03

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Intel mcs-48 manual AFN-Q1354A-03

Contents

Page MCS-48 Family of Single Chip Microcomputers Usersmanual SeptemberCredit BXPMultibus PromptTable of Contents Chapters 8051/8751/8031 MicrocomputerInsite UsersLibrary Emulation BoardEmulation Board 10-19 UPP-103 Universal Prom Programmer Packing InformationPage Ntroduction Page Introduction to MCS-48 5.0 and 10.0 J,Lsec Cycle Versions Introduction8021 is code compatible but not pin compatible with Til IntroductionEprom Introduction Architecture of a CPU Function of a ComputerTypical Computer System AccumulatorProgram Counter Jumps, Subroutines and the Stack Address Registers Three levels of subroutines may be ac- commodatedInstruction Register and Decoder Arithmetic/Logic Unit ALUTiming Control CircuitryComputer Operations Instruction FetchInput/Output Memory WriteInterrupts When finished the processor continues on To the next instructionsStep Hex Code Step No. Hex Code Assembly Code MOV RO, #32Our machine language program then becomes MOV R2, #05Cpla ADD A, REG ADD A, # ALFA*BETA/2SUB R7 Education Hardware ConfigurationDeveloping An MCS-48 Based Product Function DefinitionPrompt Intellec Development System ProductionPage Single Component MCS-4S S~stem Page Architecture SummaryArithmetic Section ~BUS Single Component System LocationSingle Component System Input/OutputSingle Component System R23 PointerJump Conditions +--1 RInterrupt Timing Clock and Timing Circuits As a TimerAs an Event Counter OscillatorALE --f---+--+ 111 InstructionLOVI BUS PCO·7 Power Down ModeRUN Stop Pin Description Prog 00-07Designation Number FunctionReset Programming, Verifying and Erasing EpromSingle Component System Single Step ResetTest and Debug Disabling Internal Program MemoryReading Internal Program Memory Program Memory Following is a functional description of the major elementsTimer/Event Counter Oscillator and ClockInput/Output Capabilities QUASI-BIDIRECTIONAL Port StructureHigh Current Outputs 1 T1 InputExpanded I/O 10 CPU ResetCarry Flag Timer Overflow Flag Jump Test Condition Instructions AccumulatorProgram Memory Functional SpecificationsData Memory Port 0 Comparator Inputs 15Timer/Event CounterOscillator and Clock See the 8021 description, .8, for a com- plete explanationExpanded 1/0 High Current OutputsTest and Interrupt Inputs 1-3 VAC Ill Analog to Digital Converter19 CPU Expanded Page Summary Expansion of Program MemoryExpanded MCS-48 System Interrupt RoutinesROM AI? LatchLatch Expansion of Data Memory IOWExpansion of Input/Output EXPAND!!D MCS-48 SystemII AA Read OO-Port #4 Write Port #5 10 or Port #6 Port #7Keyboard RD DisplayExpanded MCS-48 System Expansion Examples See Also ChapterMulti-Chip MCS-48 Systems Memory Bank Switching =====ll 8~~5BUS Port Operations Control Signal SummaryPort Characteristics Port 2 Operations000 Page Page Instruction SET Instruction SET Subroutines Instruction SET Instruction SET Summary 8021 Instruction SET Summary RETDBF Symbols and Abbreviations UsedPSW Addc A,R r Add Carry and Register Contents to Accumulator ADD A,R r Add Register Contents to AccumulatorADD A,@R r Add Data Memory Contents to Accumulator ADD A,#data Add Immediate Data to AccumulatorANL A,R r Logical and Accumulator With Register Mask Addc A,#data Add Carry and Immediate Data to AccumulatorANL A,@R r Logical and Accumulator With Memory Mask ANL A,#data Logical and Accumulator With Immediate Mask ANL A,#3+X/Y Andacc Contents with Value of EXP 3+X/YAnld Pp,A Logical and Port 4-7 With Accumulator Mask MOV RO,#50 Move 50DEC to Address Andport 4 ContentsWith ACC Bits INC RO Increment REG RET Return to Main Program11010 Flag 1 is cleared to zero F1-0 10010101111 Contents of the accumulator are cleared to zeroCpla CPL Aacc Contents are COMPLE- Mented to 11 00 0 Flag 0 is cleared to zeroADD SIX to Bits DA Aacc Adjusted to 00000001 with C SETAC 7 4 3 0 o 1 0 ADD SIX to Bits 010100001 Overflow to CExample Decrement contents of external data memory location DEC Rr Decrement Register Not in 8021Ento ClK Enable Clock Output Not in 8021,8022 EN I Enable External InterruptEN Tcnti Enable Timer/Counter Interrupt Not A,Pp Input Port or Data to AccumulatorINC Rr Increment Register INC a Increment AccumulatorINC @R r Increment Data Memory Location JBb address Jump If Accumulator Bit is Set Not in 8021 IputoPort 0 Data to Accumulator 8021, 8022 OnlyINS A,BUS Strobed Iput of BUS Data to Accumulator JC address Jump If Carry Is SetJmpp @A Indirect Jump Within JF1 address Jump If Flag 1 Is Set Not in 8021JMP address Direct Jump Within 2K Block JNC address Jump If Carry Is Not SetJNT1 address Jump If Test 1 Is Low JNI address Jump If Interrupt Input is Low Not in 8021Jnto address Jump If Test 0 Is Low Not JNZ address Jump If Accumulator Is Not ZeroJump to Location 53 DEC Jump to TimerroutineIFTF=1 Jump to CountroutineMaV A,@R r Move Data Memory Contents to Accumulator MaV A,PSW Move PSW Contents to Accumulator Not in 8021MaV A,R r Move Register Contents to Accumulator Mev A, #data Move Immediate Data to AccumulatorMev A,T Move Timer/Counter Contents to Accumulator MaV @Rr,A Move Accumulator Contents to Data Memory Movo Pp,A Move Accumulator Data to Port Movo A,Pp Move Port 4-7 Data to AccumulatorMovp A,@A Move Current Page Data to Accumulator Not in 8021 Maxdm Movx A,@R1 Move Contents of LocationMOVP3 A,@A Move Page 3 Data to Accumulator Not in 8021,8022 Current page are Moved to ACCORL A,@Rr Logical or Accumulator With Memory Mask NOP The NOP InstructionORL A,Rr Logical or Accumulator With Register Mask ORL A,#data Logical OFJ Accumulator With Immediate Mask8021 Outl Pp,A Output Accumulator Data to Port 1 or Retr Return With PSW Restore Not in 8021 Rrtc RRC a Carry is SET and ACC Rrnc RR Anew ACC Contents areExample Assume carry is not set and accumulator contains ContainsJump to Location SEL MBO Select Memory BankJMP $+20 48 HEXJump to Routine Intif ACe Stop Tcnt Stop Timer/Event-Counter10110101011 BIT 3 is SET REG 7=8Strt CNT Start Event Counter Strt T Start TimerSwap a Swap Nibbles Within Accumulator XCH A,@R r Exchange Accumulator and Data Memory Contents XCH A,R r Exchange Accumulator-Register ContentsXchd A,@R r Exchange Accumulator and Data Memory 4-Bit Data XRL A,@Rr Logical XOR Accumulator With Memory Mask XRL A,@R1 Xoracc Contents with Mask LocationXRL A,Rr Logical XOR Accumulator With Register Mask XRL A,#data Logical XOR Accumulator With Immediate MaskAppli~ation Examples Page Introduction Crystal Oscillator ModeLC Oscillator Mode Driving from External SourceReset Application Examples~~J Rvv-i T1 Multiple Interrupt Sources Tf ~r Ii6Tt-2 A7 Serves as address latch17&A3 Xtali ROM=!-39TO Both 1/0 and RAM are addressed as data memoryReset This configuration is explained in sectionF1L Expander ~fd...L Pinnumbers are Different for~1~ DB6 rAdding 8 Input Lines Application Examples ·15Adding Output for KEYBOARD/DISPLAY Scanning JfL RT T T T TApplication Examples Emulator Circuit DESCRIPTION-6 MHZ Substitute aInterface to Drum Printer RAM TimerII Keyboard Display Microwave Oven Controller Double Load Double ADDDouble Subtract Double StoreDouble Right Logical Shift Application Examples Double ExchangeDouble Left Logical Shift Double Right Arithmetic ShiftApplication Examples Binary Multiply Interrupt HandlingCPL Subtract Second from First INC Application Examples Byte Processing SystemR1,A 2sCOMPLEMENT and ADD8 MULTIPLY-ASSEMBLED by MCS-48 Macro Assembler See AP-49IIn ·1 APP\,JCATION Examples 16 x 8 DIVIDE-ASSEMBLED by MCS-48 Macro ASS.E.MBLERSEE AP-4916 x 8 DIVIDE-ASSEMBLED by MCS-48 Macro Assembler see AP-49 Page MCS-4STMComponent Page Hmos Single Component 8-BIT Microcomputer IIH!TSignal occurs once during Used to enable data ontoAddress latch enable. This Program store enable. ThisS04SH/S04SH-1 /S035HL-1/S035H L-1 Inter 8048H/8048H-1/8035HL/8035HL.1 Absolute Maximum RATINGS·Port 2 Timing BUS Timing AS a Function of TCYRead From External Data Memory S04SH/S04SH-1/S035HL/S035HL-1Waveforms 8035HL8048H/8048H·1/8035HL/8035HL·1 J3 Xtal ZPIN Configuration Logic Symbol Block Diagram RllPIN Configuration Logic Symbol Block Diagram8048/8035L/8748/8748-6/8748-8/8035/8035-8 PIN DescriptionAFN-Q1354A-03 VOL =2.0 mA All Except XTAL1, XTAL2, ResetInput High Voltage X1, X2, RESEi Output Low Voltage 10L = 1.8 mA===i---h·1 Characteristics Port 2 Timing Driving from External Source Crystal Oscillator ModeLC Oscillator Mode PROGRAMMING, VERIFYING, and Erasing the 8748 EpromTA = 2SOC ± SoC, Vee =SV ± S%, Voo = 2SV ± Verify .I.~---PROGRAM Waveforms for ProgrammingPROMPT-48 Microcomputer Design Aid, or Intel Corporation 108048/8748/8035L 108048/8748/8035L Absolute Maximum RATINGS· Operating CharacteristicsIDS0481S7481S035L BUSP1, P2BUS, P1, P2TOR Data Hold TAW Address Setup to WR260 TAD Address Setup to Data PSEN, RD to DataTpL Port 2 I/O Data Setup CharacteristicsTop Port Control Setup Before Failing Edge of Prog TA= -40·Cto +85·C, Vcc=5V ±10%, Vss=OV+-----t XTALl Crystal Oscillator Mode Driving from External SourceReset ProgTA =25C ± 5C, Vee =5V ± 5%, Vee =25V ± TA = 25C ± 5C, Vee = 5V ± 5%, Vee = 25V ±Waveforms for Programming PROMPT-48 Microcomputer Design Aid. orInter Voo Lcoscillator ModeProgramming Verification Voo Program Voltage High Level 24.0 2S.0 IPHUnit Test Conditions EA Program or Verify Voltage High Level 21.5 24.5 8748EA 5 M8048/M8748/M8035LM8048/M8748/M8035L Pin # ProgTpo Output Data Hold Time Tpp Prog Pulae Width Tcp Port Control Setup Before FallingTpL Port 2 1/0 Data Setup TLP Port 2 1/0 Data Hold 120Characteristics ALE JI ~----r---I LAN D Operati NG Characteristics BUS, P1, P2Inter 80411803118031 8049/8039 Operating Characteristics Symbol Parameter Min Max UnitALE JIL --------..1.--1----L 18049/8039 Mask Programmable ROM External ROM or Eprom MHz OperationINr IntJ18049/8039 TilVOL2 VIH1BUS, RD, WR, PSEN, ALE BUS, RD, WR, PSEN, ALE VOH1TAFC--1 I~OATING-I t=t or WaveformsTA = -400C to +850 C, Vee = Voo = +5V ±10%, Vss = OV Output Data Setup Time 230Port 2 1/0 Data Setup 300 Unit Conditions NoteCrystal Oscillator Mode LC Oscillator Mode XT AL1PIN Configuration Logic Symbol Block Diagram 8021VIH10% Input high voltage all except Xtal 1 OC to 70CV1Hl Input High Voltage Xtal 1 & 2, T1 T1, RESElALE XTAL28022 VTH Reset AvssProg POO-P07 Varef ANO,AN1 ALE Xtal8022 FzxIpAL---ooj·1 Port 2 TimingAID Converter Characteristics Analog Input TimingMnemonic for in-page Operation Analog Input 0, Analog Input TimerCNT Inter PIN Description GNDAbsolute Maximum Ratings ~~x 125 P20-P23 -- .....--X..... ...Jr 108243 14P5218243 GND18243 Tes # pins= 60 mA-+- 8 mA/pin = 7.5= 1 2 3 4 5 6 7 8 9 10 11 12Output Expander Timing 16,384·8IT ROM with CE2 ResetCE1 ReadyIII Symbol Parameter MIN MAX8355/8355-2 ILO+- Al ~ Cl ~Output Mode Input Mode8355/8355·2 PIN Configuration Block Diagram Directly Compatible with SOS5A CPU8755AFUNCTIONAL PIN Definition 8755APROG/CE1 UPPI41 SA Programming Module Cross Reference Module Name USE withUPP UPP UP2121Comment Symbol Parameter MIN MAX VIL8755A Ready Hold TimeClock Specification for 8755A Prom Read, 1/0 Read and Write TimingWait State Timing Ready =0 ITA =OC to 70C Vee =5V ± 5% Vss =OV Specification ProgrammingVoo Programming Voltage during Write To Eprom Program Mode Timing Diagram 8155-2 Enable8085A 8085A-2 8156-28155/8156/8155-2/8156-2 Timer OUT8155/8156 PIN Functions Description 8156 Internal RegistersProgramming Command Register Reading the Status RegisterBFLowLow INTRLowHigh Control Input Mode Output ModeINPUT/OUTPUT Section STB8155/8156/8155-2/8156-2 PcaTimer Section Example Program Interval Timer Interrupt Levels 8085A Minimum System ConfigurationWR AD ALE Symbol Parameter MIN MAX Units Test Conditions VIL Symbol Parameter MIN MAX UnitsRead Cycle Write Cycle8155/8156/8155-2/8156-2 WI\ J / jBasic Input Mode Basic Output ModePIN Configuration Block Diagram PIN NamesOperational Description Truth Table for Power Down and Function Enable8185/8185-2 Truth Table for Control and Data BUS PIN StatusAbsolute Maximum Ratings Comment8185/8185-2 Page Page SINGLE-COMPONENT 8-BIT Microcomputer MACRO-VIEW of the 8051 Architecture 0INTRODUCTION8051 Family 8051 CPU Architecture1Interrupt System ON-CHIP Peripheral Functions21/0 Facilities 8031/8051/8751 3Timer/Event Counters 8031/8051/87518031/8051/8751 4Serial Communications~=- J~~====~ ~DATA 8031/8051/8751 Circuit ground potentialXTAL2 PsenXTAL1 Family Development System and Software SupportWorkshop Symbol Parameter Min Typ Max UnitsUniversal Prom Programmer Personality Card UPP-851 Insite Library12MHz Clock Data Memory Write Cycle Inter8031/8051/8751 8051 Instruction SET SummaryInter All mnemonics copyrlghted@ Intel CorporationPage Compatible MCS-48 Components PIN Configuration 1024 X 4 BIT Static RAM2114A Family Address -..II-------------i--l Symbol ParameterUnit Typical D.C. and .A.C. Characteristics Normauzed Access Time VS Supply Voltage2316E 16K 2K 8 ROM 2316E Data ----=HIGHZ~--~~~~~~~~~~-OU-T~TV-ALIO~~~JlJJI PIN Configuration PIN Connection During Read or ProgramFamily BB Power Supply 5V±5% 5Vt.5% -5V±5% -5V±10%Operating Characteristics Nco and A.C.OPERATING Conditions During ReadInput Capacitance Address to Output Delay2708·1 limits 2708·6Limits Units VIN = OVFamily WaveformsPIN Configuration Mode Selection PIN NamesProgramming CE = VIH. OE = VIL2716 Cout2716 Typical 16K Eprom System2716 Device OperationTwo Line Control Approved8086·2 MPU .. .Zero Wait State Industry Standard Pinout . .. Jedec8205 Ei==~ fEH2·E3 Applications A13 --..,-H+-q E8205 Eii-+-IH-+t-t rState Decoder Circuit TA = O·Cto + 75·C, Vee = 5V ± 5% Typical Characteristics\.. ~ ~ MIN MAXConditions of Test Test Load Switching CharacteristicsCharactristics Test WaveformsGD ~s ------- + H PIN Configuration Logic DiagramIT os DB ---------- -- +i+-+1 Functional DescriptionIl D IE DGated Buffer Basic Schematic SymbolsII. Gated Butter 3-State DS2 , ------,----.J8212 Here the 8212 is used as the status latch for an 8080A VI. Output Port With Hand-Shaking~DI, Stbdo LOW Order AD2Bossa AD4 AD5 AD6 AD7 CLRInput Load Current, ACK, OS2, CR VF = A5V 8212Output Currents 100mA IOL = 15mAFfi Ili052. CK. ACK. DI1-Dls Input Capacitance 5pF Switching CharacteristicsTyp. Max CIN 051 MD Input Capacitance 9pF 12pF DOs Output Capacitance 8pFTCI II,D SGS821413214 Icex8214/3214 CapacitancesInte Test Conditions Test Load Circuit·BITPARALLEL Bidirectional BUS Driver 001Bidirectional Driver Control aatlng OlEN, CSWaveforms Characteristics OUT O---TIFI IF2 IRI IR2 VIL VIH Voli VOL2821618226 Applications of the 8216/8226010 8282/8283Octal Latch VCCPIN Definitions Operational Description PinD.scrlptlonTshov VOL VOHTivov TehozJJ\~ J/~~ 8282/8283 Intel VeeAo-A7 Bo- B7Characteristics for 8286/8287 Output Delay vs. Capacitance Jk~Output Page Page Synchronous and Asynchronous Operation Synchronous 5·8 Bit CharactersFeatures and Enhancements Capacitance pF CapacitanceIofl Bus Parameters !Note Input Waveforms for AC TestsMIN MAX Unit Programmable Interval Timer General VIIi -.,--.,qSystem Interface Control Word RegisterProgramming Operational DescriptionGeneral Control Word Format825318253·5 Mode 2 Rate Generator =41 I---t--n --+LSB 8253/8253-5MSB Read Operations Read Operation ChartMode Register for Latching Count Reading While CountingOe to 700 e Re.dCycle Bus Parameters NoteInput Waveforms for A.C. Tests Write Timing825318253·5 Clock and Gate TimingPIN Configuration 8255A Block Diagram Programmable Peripheral Interface8255A Basic Operation 8255A18255A·58255A Functional Description Face peripheral devices or structuresGroup a and Group B Controls PIN Configuration PIN Names8255A18255A·5 Ports A, B, and CSingle Bit Set/Reset Feature Mode Selection8255A Operational Description Operating Modes Interrupt Control FunctionsMode 0 Port Definition Mode 0 Configurations8255AJ8255A·5 PA7·pAoII I I I, I0 I0 I0 IBF Input Buffer Full F/F Input Control Signal DefinitionTPH Intr Interrupt RequestIntea Output Control Signal Definition10 I ·IOMXlXl Inte BOutput Operations Combinations of ModeBidirectional Bus 1/0 Control Signal Definition Input Operations8255.Al8255A·5 LtAOiErXtJ I 0\ \, I, erXtJ I0\30AFN-00744A-14 Mode Definition SummaryOnly Applications of the 8255A Printer InterfacePC, r MSBCapacitance Read MIN. MAX UnitCIR TwB TRIT LtR1BjSIB-Ii Programmable Interrupt Controller SP/ENInterrupts in Microcomputer Systems 8259A8259A Basic Functional Description Interrupt Mask Register IMR Interrupt Request Register IRR and IN·SERVICE Register ISRPriority Resolver INT InterruptCascade BUFFER/COMPARATOR 8259A8259A Interface to Standard System Bus Interrupt Sequence~O ~ ~ General Disable FunctionProgramming the 8259A Input Operation ReadInitialization Command Words 1 and 2 ICW1,ICW2 Initialization Command Word 3 ICW30 I 0 I 0 I 0 I 0 lID, liD, lIDo 8259AOperation Control Word 2 OCW2 Operation Control Words Ocwi Operation Command Words OCWsOperation Control Word 1 OCW1 OcwaOJNTl Operation Command Word FormatR,-r-- I-i-Ioo r,-r,-r Fully Nested Mode Special Mask ModeBuffered Mode Special Fully Nested ModeRotating Priority Mode B Rotation by Software Word enabled onto the data bus during m5 isAutomatic END of Interrupt Aeoi Mode WolThis mode is programmed using bit 3 in ICW1 Priority Cell Simplified Logic DiagramLevel Triggered Mode OH-++-+8272 Registers CPU Interface Features8272 Description8272 Polling Feature Reset to the Interrupt signalIntJ Command SET Command Descriptions Read DataWrite Data Transfer Capacity EN End of Cylinder Flag No No Data FlagRead a Track Write Deleted DataRead Deleted Data ReadidScan Commands Specify RecalibrateSense Interrupt Status Sense Drive StatusStatus Registers BIT Name Symbol Description UsaCINI» DC CharacteristicsVIL CLK & WR CLK VIH VIN=OVICY ~-----~---V Sel-I Timing Measurement ConditionsLI3 Block Oiagram8273, 8273·4, 8273·8 Brief Description of HDLC/SDLC Protocols32XCLi Flag DETProgrammable KEYBOARD/DISPLAY Interface RAMHardware Description 827918279-5Principles of Operation 827918279·5 Software Operation Data Read End Interrupt/Error Mode SetStatus Word Data WriteInterface Considerations Scanned Keyboard Mode, 2·Key Lockout===~ General Block Diagram ApplicationsVIL2 Symbol Test TYP MAXIIL1 Input Waveforms for A.C. Tests BUS Parameters8279 Scan Timing Scan Waveforms Display WaveformsGpib TALKER/LISTENER 8291 General Purpose Interface BUS Gpib System Diagram8291 General DescriptionAcrs AcdsPacs PpasRemote Messages Received ATN SH,AH,T,TE,L,LE,PP,C DAB SH,AH,T,TE,L,LE,SR,RL,PP,CAH,C DACDAV Remote Messages Sent ATN DABDAC ENDAll Write Registers DontCareSPAS---SPAS Spasc Llcno LLO Lloc Interrupt RegistersMenting this feature, with 80 and Bi enabied from ITO ILO I 0 I 0 I 0 I 0 Admi Aomoi Provided for Command Pass Through RegisterSection on Parallel Poll Protocol Auxiliary Mode Register Auxiliary CommandsAuxiliary Register a Internal Counter2NF Auxiliary Register BReset Procedure Parallel Poll Protocol8291 Using DMA 8291 to 8291A Software Compatibility Ilol Device Electrical CharacteristicsVOH-INT IlohTwA~ Timing WaveformsGpib Timingsii Modified State Diagrams Figure A.1 State Diagrams next101 Response to ATN 200ns Interface Message Accept Time t Settling Time for Multiline Messages 21stTE,L,LE,C,CE Figure C-l -Wire Handshake Timing at Appendix CFigure C.2. Handshake Flowchart IIIL---,--11 ,--I 105Gpib Controller 106Ai1W Gpib Transceiver BUS9 EOIBUS1 OATA1Gpib Mode 0 PIN Description=OV NDAC* I/OTIL NrfoIeee Gpib Mode 2 PIN Description Mode 1 PIN DescriptionNdac Nrfd IeeeMode 3 PIN Description R1L LIENTiR1 Absolute Maximum Ratings Operating Characteristics8293 CapacitanceTYP.· MAX CharacteristicsTA = O·Cto 70·C Vee= 5.0V ± 10% GND = OV ·118Output Loading Test Circuits 8293 Waveforms8294 8295 ·122====J 123UPI·41A Features Enhancements Mnemonic Description Bytes Cycles Signal DescriptionData Moves 8041 Al8641 Al8741 a VIU IU1Read OPERATION-DATA BUS Buffer Register Input and Output Waveforms for A.C. TestsTypical 8041/8741A Current Write OPERATION-DATA BUS Buffer RegisterCHARACTERISTICS-DMA CHARACTERISTICS-PORTWAVEFORMS-DMA PROGRAMMING, VERIFYING, and Erasing the 8741A Eprom VOOSpecification for Programming Timing Specification for ProgrammingVdol Program 8041Al8641 Al8741ASupport Products Page Microcomputer Development System CreditMODEL225 Functional Description 10-2Peripheral Interface InterMODEL225 System ComponentsIntegral CRT ControlSpecifications 9800556 Notavailable on bus110V, 60 Hz 5.9 Amp 220V, 50 Hz 3.0 Amp 9800292Page Intellec Prompt MCS·48 Microcomputer Design AID Intellec Prompt Features Single Component Compu.terPrompt 48 Commands and Functions Intellec PromptIntellec Prompt Functional Description MCS-48 ProcessorsPrompt system Is running a user program User Interrupt causes an Interrupt only IfCycle Time tCY = 2.5,..s Clock 6 MHz ± 0.1% Ordering Information MCS·48 IN·CIRCUIT Emulator ~ L · ICE·49Memory Mapping GO from .START Till XDATA. Rslt WrittenICE·49 ISIS·IIEM1 Emulation Board EM1 Ordering Information EM1 SpecificationsDC Power Vcc5V ±5% Icc 300 mA max MDS·EM1EM2 Emulation Board ANO 40·PIN Socket Configuration EM2 Block DiagramEM2 AN1UPP-1P3 EM2MDS-EM2 Canadian Sales Offices SeptemberCanadian Distributors TAvnet Electronics McCormick Avenue Costa MesaIntJ Bowers Avenue International Sales and Marketing Offices International DISTRIBUTORS/REPRESENTATIVESInternational Sales and Marketing Offices INTEL$ Marketing OfficesCanadian Service Offices