Intel mcs-48 manual Inter8031/8051/8751, Instruction SET Summary

inter8031/8051/8751

TABLE 2-1 8051 INSTRUCTION SET SUMMARY

Notes on instruction set and addressing modes:

Rn	- Register R7-RO of the currently selected Register Bank.
data	-8-oit internal data location'saddress. This could be an
	Internal Data Ram location (0-127) or a SFR (i.e. I/O
	port, control register, status register, etc. (128-255).
@Ri	-8-bil Internal Data RAM location (!f-255) addressed in-
	directly through register Rl or RO.
#data	-8-bit constant included in instruction.
#datal6 -1~bitconstant included in instruction.
addr16	-16-bit destinatien address. Used by LCALL & LJMP. A
	branch can be anywhere within the 64K-byte Program
	Memory address space.
addrll	-II-bit destination address. Used by ACALL &AJMP. The
	branch will be within the same 2K-byte page of program
	memory as the first byte of the following instruction.
rei	-Signed (two'scomplement) 8-bit offset byte. Used by
	SJMP and all conditional jumps. Range is -128 to +127
	bytes relative to first byte of the following Instruction.
bit	-Direct Addressed bit in Internal Data RAM or Special
	Function Register.
	- New operation not provided by 8048/8049.

Data Transfer

Interrupt Response Timf3: To finish execution of current instruction, respond to the interrupt request, push the PC and to vector to the first

instruction of the interrupt service program requires 38 to 81 oscillator

periods (3 to 7 ps @12MHz).

INSTRUCTIONS THAT AFFECT FLAG SETTINGS'

INSTRUCTION		FLAG		INSTRUCTION	FLAG
	C	OV	AC		C OV AC
ADD	X	X	X	CLR C	0
AD DC	X	X	X	CPL C	X
SUBB	X	X	X	ANL C, bit	X
MUL	0	X		ANL C,Ibit	X
DIV	0	X		ORL C, bit	X
DA	X			ORL C,Ibit	X
RRC	X			MOV C, bit	X
RLC	X			CJNE	X
SETB C	1

'Notethat operations on SFR byte address 208 or bit addresses 209- 215 (I.e. the PSW or bits in the PSW) will also affect flag settings.

Logic

Mnemonic	Description
MOV A,Rn	Move register to A
'MOV A,data	Move direct byte to A
MOV A,@Ri	Move indirect RAM to A
MOV A,#data	Move immediate data to A
MOV Rn,A	Move A to register
'MOV Rn,dala	Move direct byte to register
MOV Rn,#data	Move immediate data to
	register
'MOV data,A	Move A to direct byte
'MOV data,Rn	Move register to direct byte
'MOV data,data	M6ve direct byte to direct
	byte
'MOV data,@Ri	Move indirect RAM to direct
	byte
'MOV data,#data	Move immediate data to
	direct byte
MOV@Ri,A	Move A to indirect RAM
'MOV @Ri.data	Move direct byte to indirect
	RAM
MOV @Ri,#data	Move immediate data to
	indirect RAM

Oscillalor

Bytes Periods

112

12

12

12

12

24

12

12

24

24

24

24

12

24

12

			Oscillator
Mnemonic	Description	Bytes	Periods
ANL A,Rn	AND register 10 A	1	12
'ANLA.data	AND direcl byte to A		12
ANL A,@Ri	AND indirect RAM to A		12
ANL A,#dala	AND immediate data to A		12
'ANLdata,A	AND A to direct byte		12
'ANLdata,#data	AND immediate data to direct		24
	byte
'ANLG,bit	AND direct bit to carry		24
'ANLC,Ibit	AND complement of direct bit		24
	to carry
ORL A,Rn	OR reg ister to A		12
'ORLA,data	OR direct byte to A		12
ORL A,@Ri	OR indirect RAM to A		12
ORL A,#data	OR immediate data to A		12
'ORLdataA	OR A to direct byte		12
'ORLdata,#data	OR immediate data to direct		24
	byte
'ORLC,bit	OR direct bit to carry		24
'ORLC,Ibit	OR complement of direct bit		24
	to carry
XRL A,Rn	Exclusive-OR register to A		12

'MOV DPTR,	Move 16-bit constant to Data	24
#datal6	Pointer
'MOV C,bit	Move direct bit to carry	12
'MOV bit,C	Move carry to di rect bit	24
'MOVC A,@A+	Move Program Memory byte	24
DPTR	addressed by A+DPTR to A
'MOVC A,@A+PC	Move Program Memory byte	24
	addressed by A+PC to A
MOVX A,@Ri	Move External Data (8-bil	24
	address) to A
'MOVX A,@DPTR	Move External Data (16-bit	24
	address) to A
MOVX @Ri,A	Move A to External Data	24
	(8-bit address)
'MOVX @DPTR,A	Move A to External Data	24
	(16-bit address)
'PUSHdata	Move direct byte to stack	24
	and inc. SP
'POPdata	Move direct byte from stack	24
	and dec. SP
XCH A,Rn	Exchange register with A	12
'XCHAdata	Exchange direct byte with A	12
XCH A,@Ri	Exchange indirect RAM	12
	with A
XCHD A,@Ri	Exchange indirect RAM's	12
	least sig nibble with A'sLSN

'XRLA,data	Exclusive-OR direct byte to A		12
XRL A,@Ri	Exclusive-OR indirect RAM		12
	to A
XRL A,#data	Exclusive-OR immediate		12
	data to A
'XRLdata,A	Exclusive-OR A to direct byte		12
, XRL data,#data	Exclusive-OR immediate		24
	data to direct byte
'SETBC	Set carry		12
'SETSbit	Set direct bit		12
CLR A	Clear A		12
CLR C	Clear carry		12
'GLRbit	Clear direct bit		12
CPL A	Complement A		12
CPL C	Complement carry		12
'CPLbit	Complement direct bit		12
RL A	Rotate A Left	·1	12
RLC A	Rotate A Left through carry		12
RR A	Rotate A Right		12
RRC A	Rotate A Right through carry		12
SWAP A	Rotate A left four (exchange		12
	nibbles wi.thin A)

All mnemonics copyrlghled@ Intel Corporation 1980.

AFN-01462A-14

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