Intel mcs-48 manual Signal Description, Mnemonic Description Bytes Cycles, Data Moves

Models: mcs-48

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8041 AJ8641AJ8741 A

PIN DESCRIPTION

Signal Description

00- 0 7 Three·state, bidirectional DATA BUS BUFFER lines

(BUS)

used to interface the UPI·41A to an 8·bit master

 

system data bus.

P 10-P 17

8·bit, PORT 1 quasi·bidirectionall/O lines.

P20-P27 8·bit,PORT 2 quasi·bidirectionall/Olines. The lower

4bits (P20-P23)interface directly to the 8243 I/O ex· pander device and contain address and data infor· mation during PORT 4-7 access. The upper 4 bits

(P24-P27) can be programmed to provide Interrupt Request and DMA Handshake capability. Software

control can configure P24 as OBF (Output Buffer Full), P25 as IBF (Input Buffer Full~as DRQ (DMA Request), and P27 as DACK (DMA ACKnowledge).

WR

I/O write input which enables the master CPU to

 

write data and command words to the UPI·41A IN·

 

PUT DATA BUS BUFFER.

RD

110 read input which enables the master CPU to

 

read data and status words from the OUTPUT DATA

 

BUS BUFFER or status register.

CS

Chip select input used to select one UPI·41Aout of

 

several connected to a common data bus.

Ao

Address input used by the master processor to in·

 

dicate whether byte transfer is data or command.

TEST 0,

Input pins which can be directly tested using condi·

TEST 1

tional branch instructions.

 

T1 also functions as the event timer input (under

 

software control). To is used during PROM program·

 

ming and verification in the 8741A.

XTAL 1,

Inputs for a crystal, LC or an external timing signal

XTAL2

to determine the internal oscillator frequency.

SYNC

Output signal which occurs once per UPI·41A in·

 

struction cycle. SYNC can be used as a strobe for

 

external circuitry; it is also used to synchronize

 

single step operation.

EA

External access input which allows emulation,

 

testing and PROM/ROM verification.

PROG

Multifunction pin used as the program pulse input

 

during PROM programming.

 

During I/O expander access the PROG pin acts as

 

an address/data strobe to the 8243.

RESET

Input used to reset status flip·flops and to set the

 

program counter to zero.

 

RESET is also used during PROM programming and

 

verification.

SSSingle step input used in the 8741A in conjunction with the SYNC output to step the program through each instruction.

Vee

+ 5V main power supply pin.

Voo

+ 5V during normal operation. + 25V during pro·

 

gramming operation. Low power standby pin in

 

ROM version.

Vss

Circuit ground potential.

UPITM INSTRUCTION SET

Mnemonic Description Bytes Cycles

ACCUMULATOR

ADD

A.Rr

Add register to A

1

1

ADD

A.@Rr

Add data memory to A

1

1

ADD A.#data

Add immediate to A

2

2

ADDC A.Rr

Add register to A with carry

1

1

ADDC A.@Rr

Add data memory to A with carry

1

1

ADDC Mdata

Add immed. to A with carry

2

2

ANL A.Rr

AND register to A

1

1

ANL A.@Rr

AND data memory to A

1

1

ANL A.#data

AND immediate to A

2

2

ORl A.Rr

OR register to A

1

1

ORL A.@Rr

OR data memory to A

1

1

ORL A.#data

OR immediate to A

2

2

XRl A.Rr

Exclusive OR register to A

1

1

XRL A.@Rr

Exclusive OR data memory to A

1

1

XRL A.#data

Exclusive OR immediate to A

2

2

INC A

Increment A

1

1

DEC A

Decrement A

1

1

CLR A

Clear A

1

1

CPL A

Complement A

1

1

DA A

Decimal Adjust A

1

1

SWAP A

Swap nibbles of A

1

1

RL A

Rotate A left

1

1

RlC A

Rotate A left through carry

1

1

RR A

Rotate A right

1

 

RRC A

Rotate A right through carry

1

 

INPUT/OUTPUT

IN A.Pp

Input port to A

 

2

OUTL Pp.A

Output A to port

 

2

ANl Pp.#data

AND Immediate to port

 

2

ORl Pp.#data

OR immediate to port

 

2

IN A.DBB

Input DBB to A. clear IBF

 

1

OUT DBB.A

Output A to DBB. set OBF

 

1

MOV STS,A

A4-A7 to Bits 4-7of Status

 

1

MOVD A.Pp

Input Expander port to A

 

2

MOVD Pp.A

Output A to Expander port

 

2

ANlD Pp.A

AND A to Expander port

 

2

ORlD Pp.A

OR A to Expander port

 

2

DATA MOVES

 

 

 

MOV A.Rr

Move register to A

1

1

MOV A.@Rr

Move data memory to A

1

1

MOV A.#data

Move Immediate to A

2

2

MOV Rr.A

Move A to register

1

1

MOV @Rr.A

Move A to data memory

1

1

MOV Rr.#data

Move immediate to register

2

2

MOV @Rr.#data

Move Immediate to data memory

2

2

MOV A.PSW

Move PSW to A

1

1

MOV PSW.A

Move A to PSW

1

1

XCH A.Rr

Exchange A and register

1

1

XCH A.@Rr

Exchange A and data memory

1

1

XCHD A.@Rr

Exchange digit of A and register

1

1

MOVP A.@A

Move to A from current page

1

2

MOVP3. A.@A

Move to A from page 3

1

2

TIMER/COUNTER

 

 

MOV A.T

Read Timer/Counter

 

 

MOV T.A

Load Timer /Counter

 

 

STRT T

Start Timer

 

 

STRT CNT

Start Counter

 

 

STOP TCNT

Stop Timer /Counter

 

 

EN TCNTI

Enable Timer /Counter Interrupt

 

 

DIS TCNTI

Disable Timer /Counter Interrupt

 

 

9-125

00188A

 

Page 440
Image 440
Intel mcs-48 manual Signal Description, Mnemonic Description Bytes Cycles, Data Moves