Intel mcs-48 manual

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Intel mcs-48 manual

Contents

Page MCS-48 Family of Single Chip Microcomputers Usersmanual September BXP MultibusCredit Prompt Table of Contents Chapters 8051/8751/8031 Microcomputer Emulation Board Emulation Board 10-19 UPP-103 Universal Prom ProgrammerInsite UsersLibrary Packing InformationPage Ntroduction Page Introduction to MCS-48 8021 is code compatible but not pin compatible with Introduction5.0 and 10.0 J,Lsec Cycle Versions Eprom IntroductionTil Introduction Function of a Computer Typical Computer SystemArchitecture of a CPU Accumulator Program Counter Jumps, Subroutines and the Stack Three levels of subroutines may be ac- commodated Instruction Register and DecoderAddress Registers Arithmetic/Logic Unit ALU Control Circuitry Computer OperationsTiming Instruction Fetch Interrupts Memory WriteInput/Output When finished the processor continues on To the next instructions Step No. Hex Code Assembly Code MOV RO, #32 Our machine language program then becomesStep Hex Code MOV R2, #05 SUB R7 ADD A, # ALFA*BETA/2Cpla ADD A, REG Hardware Configuration Developing An MCS-48 Based ProductEducation Function Definition Prompt Intellec Development System ProductionPage Single Component MCS-4S S~stem Page Arithmetic Section SummaryArchitecture ~BUS Single Component System Location Single Component System Input/Output Single Component System R23 Pointer Jump Conditions +--1 R Interrupt Timing As a Timer As an Event CounterClock and Timing Circuits Oscillator ALE --f---+--+ 111 Instruction LOVI RUN Stop Power Down ModeBUS PCO·7 Pin Description 00-07 DesignationProg Number Function Reset Programming, Verifying and Erasing Eprom Single Component System Reset Test and DebugSingle Step Disabling Internal Program Memory Reading Internal Program Memory Program Memory Following is a functional description of the major elements Timer/Event Counter Oscillator and Clock Input/Output Capabilities QUASI-BIDIRECTIONAL Port Structure Expanded I/O 1 T1 InputHigh Current Outputs Reset Carry Flag Timer Overflow Flag10 CPU Jump Test Condition Instructions Accumulator Data Memory Functional SpecificationsProgram Memory 15Timer/Event Counter Oscillator and ClockPort 0 Comparator Inputs See the 8021 description, .8, for a com- plete explanation Test and Interrupt Inputs High Current OutputsExpanded 1/0 1-3 VAC Ill Analog to Digital Converter 19 CPU Expanded Page Summary Expansion of Program Memory Expanded MCS-48 System Interrupt Routines Latch AI? LatchROM Expansion of Data Memory IOW Expansion of Input/Output EXPAND!!D MCS-48 System II AA Read OO-Port #4 Write Port #5 10 or Port #6 Port #7 Keyboard RD Display Expanded MCS-48 System Expansion Examples See Also Chapter Multi-Chip MCS-48 Systems Memory Bank Switching =====ll 8~~5 Control Signal Summary Port CharacteristicsBUS Port Operations Port 2 Operations 000 Page Page Instruction SET Instruction SET Subroutines Instruction SET Instruction SET Summary 8021 Instruction SET Summary RET PSW Symbols and Abbreviations UsedDBF ADD A,R r Add Register Contents to Accumulator ADD A,@R r Add Data Memory Contents to AccumulatorAddc A,R r Add Carry and Register Contents to Accumulator ADD A,#data Add Immediate Data to Accumulator ANL A,@R r Logical and Accumulator With Memory Mask Addc A,#data Add Carry and Immediate Data to AccumulatorANL A,R r Logical and Accumulator With Register Mask Anld Pp,A Logical and Port 4-7 With Accumulator Mask ANL A,#3+X/Y Andacc Contents with Value of EXP 3+X/YANL A,#data Logical and Accumulator With Immediate Mask Andport 4 Contents With ACC BitsMOV RO,#50 Move 50DEC to Address INC RO Increment REG RET Return to Main Program 10010101111 Contents of the accumulator are cleared to zero Cpla CPL Aacc Contents are COMPLE- Mented to11010 Flag 1 is cleared to zero F1-0 11 00 0 Flag 0 is cleared to zero DA Aacc Adjusted to 00000001 with C SET AC 7 4 3 0 o 1 0 ADD SIX to Bits 010100001ADD SIX to Bits Overflow to C Example Decrement contents of external data memory location DEC Rr Decrement Register Not in 8021 EN I Enable External Interrupt EN Tcnti Enable Timer/Counter Interrupt NotEnto ClK Enable Clock Output Not in 8021,8022 A,Pp Input Port or Data to Accumulator INC @R r Increment Data Memory Location INC a Increment AccumulatorINC Rr Increment Register IputoPort 0 Data to Accumulator 8021, 8022 Only INS A,BUS Strobed Iput of BUS Data to AccumulatorJBb address Jump If Accumulator Bit is Set Not in 8021 JC address Jump If Carry Is Set JF1 address Jump If Flag 1 Is Set Not in 8021 JMP address Direct Jump Within 2K BlockJmpp @A Indirect Jump Within JNC address Jump If Carry Is Not Set JNI address Jump If Interrupt Input is Low Not in 8021 Jnto address Jump If Test 0 Is Low NotJNT1 address Jump If Test 1 Is Low JNZ address Jump If Accumulator Is Not Zero Jump to Timerroutine IFTF=1Jump to Location 53 DEC Jump to Countroutine MaV A,PSW Move PSW Contents to Accumulator Not in 8021 MaV A,R r Move Register Contents to AccumulatorMaV A,@R r Move Data Memory Contents to Accumulator Mev A, #data Move Immediate Data to Accumulator Mev A,T Move Timer/Counter Contents to Accumulator MaV @Rr,A Move Accumulator Contents to Data Memory Movp A,@A Move Current Page Data to Accumulator Movo A,Pp Move Port 4-7 Data to AccumulatorMovo Pp,A Move Accumulator Data to Port Maxdm Movx A,@R1 Move Contents of Location MOVP3 A,@A Move Page 3 Data to Accumulator Not in 8021,8022Not in 8021 Current page are Moved to ACC NOP The NOP Instruction ORL A,Rr Logical or Accumulator With Register MaskORL A,@Rr Logical or Accumulator With Memory Mask ORL A,#data Logical OFJ Accumulator With Immediate Mask 8021 Outl Pp,A Output Accumulator Data to Port 1 or Retr Return With PSW Restore Not in 8021 Rrnc RR Anew ACC Contents are Example Assume carry is not set and accumulator containsRrtc RRC a Carry is SET and ACC Contains SEL MBO Select Memory Bank JMP $+20Jump to Location 48 HEX Stop Tcnt Stop Timer/Event-Counter 10110101011Jump to Routine Intif ACe BIT 3 is SET REG 7=8 Swap a Swap Nibbles Within Accumulator Strt T Start TimerStrt CNT Start Event Counter Xchd A,@R r Exchange Accumulator and Data Memory 4-Bit Data XCH A,R r Exchange Accumulator-Register ContentsXCH A,@R r Exchange Accumulator and Data Memory Contents XRL A,@R1 Xoracc Contents with Mask Location XRL A,Rr Logical XOR Accumulator With Register MaskXRL A,@Rr Logical XOR Accumulator With Memory Mask XRL A,#data Logical XOR Accumulator With Immediate Mask Appli~ation Examples Page Crystal Oscillator Mode LC Oscillator ModeIntroduction Driving from External Source Reset Application Examples ~~J Rvv-i T1 Multiple Interrupt Sources Tf ~r Ii6 17&A3 Serves as address latchTt-2 A7 Xtali ROM =!-39TO Both 1/0 and RAM are addressed as data memory F1L This configuration is explained in sectionReset Expander ~fd...L Pinnumbers are Different for ~1~ DB6 r Adding 8 Input Lines Application Examples ·15 Adding Output for KEYBOARD/DISPLAY Scanning JfL RT T T T T Application Examples Emulator Circuit DESCRIPTION-6 MHZ Substitute a Interface to Drum Printer II Keyboard Display TimerRAM Microwave Oven Controller Double ADD Double SubtractDouble Load Double Store Application Examples Double Exchange Double Left Logical ShiftDouble Right Logical Shift Double Right Arithmetic Shift Application Examples Binary Multiply Interrupt Handling Application Examples Byte Processing System R1,ACPL Subtract Second from First INC 2sCOMPLEMENT and ADD 8 MULTIPLY-ASSEMBLED by MCS-48 Macro Assembler See AP-49 IIn ·1 APP\,JCATION Examples 16 x 8 DIVIDE-ASSEMBLED by MCS-48 Macro ASS.E.MBLERSEE AP-49 16 x 8 DIVIDE-ASSEMBLED by MCS-48 Macro Assembler see AP-49 Page MCS-4STMComponent Page Hmos Single Component 8-BIT Microcomputer IIH!T Used to enable data onto Address latch enable. ThisSignal occurs once during Program store enable. This S04SH/S04SH-1 /S035HL-1/S035H L-1 Inter 8048H/8048H-1/8035HL/8035HL.1 Absolute Maximum RATINGS· Port 2 Timing BUS Timing AS a Function of TCY S04SH/S04SH-1/S035HL/S035HL-1 WaveformsRead From External Data Memory 8035HL 8048H/8048H·1/8035HL/8035HL·1 J3 Xtal Z PIN Configuration Logic Symbol Block Diagram Rll PIN Configuration Logic Symbol Block Diagram 8048/8035L/8748/8748-6/8748-8/8035/8035-8 PIN Description AFN-Q1354A-03 All Except XTAL1, XTAL2, Reset Input High Voltage X1, X2, RESEiVOL =2.0 mA Output Low Voltage 10L = 1.8 mA ===i---h·1 Characteristics Port 2 Timing Crystal Oscillator Mode LC Oscillator ModeDriving from External Source PROGRAMMING, VERIFYING, and Erasing the 8748 Eprom TA = 2SOC ± SoC, Vee =SV ± S%, Voo = 2SV ± PROMPT-48 Microcomputer Design Aid, or Waveforms for ProgrammingVerify .I.~---PROGRAM Intel Corporation 108048/8748/8035L 108048/8748/8035L Operating Characteristics IDS0481S7481S035LAbsolute Maximum RATINGS· BUSP1, P2BUS, P1, P2 TAW Address Setup to WR 260 TAD Address Setup to DataTOR Data Hold PSEN, RD to Data Characteristics Top Port Control Setup Before Failing Edge of ProgTpL Port 2 I/O Data Setup TA= -40·Cto +85·C, Vcc=5V ±10%, Vss=OV Crystal Oscillator Mode Driving from External Source Reset+-----t XTALl Prog TA =25C ± 5C, Vee =5V ± 5%, Vee =25V ± TA = 25C ± 5C, Vee = 5V ± 5%, Vee = 25V ± Waveforms for Programming PROMPT-48 Microcomputer Design Aid. or Inter Programming Verification Lcoscillator ModeVoo IPH Unit Test ConditionsVoo Program Voltage High Level 24.0 2S.0 EA Program or Verify Voltage High Level 21.5 24.5 8748 EA 5 M8048/M8748/M8035L M8048/M8748/M8035L Pin # Prog Tcp Port Control Setup Before Falling TpL Port 2 1/0 Data SetupTpo Output Data Hold Time Tpp Prog Pulae Width TLP Port 2 1/0 Data Hold 120 Characteristics ALE JI ~----r---I L AN D Operati NG Characteristics BUS, P1, P2 Inter 80411803118031 8049/8039 Operating Characteristics Symbol Parameter Min Max Unit ALE JIL --------..1.--1----L 18049/8039 Mask Programmable ROM External ROM or Eprom MHz Operation INr IntJ18049/8039 Til VIH1 BUS, RD, WR, PSEN, ALEVOL2 BUS, RD, WR, PSEN, ALE VOH1 TAFC--1 I~OATING-I t=t or Waveforms Output Data Setup Time 230 Port 2 1/0 Data Setup 300TA = -400C to +850 C, Vee = Voo = +5V ±10%, Vss = OV Unit Conditions Note Crystal Oscillator Mode LC Oscillator Mode XT AL1 PIN Configuration Logic Symbol Block Diagram 8021 OC to 70C V1Hl Input High Voltage Xtal 1 & 2, T1VIH10% Input high voltage all except Xtal 1 T1, RESEl ALE XTAL2 8022 Reset Avss Prog POO-P07VTH Varef ANO,AN1 ALE Xtal 8022 Fzx IpAL---ooj·1 Port 2 Timing AID Converter Characteristics Analog Input Timing CNT Analog Input 0, Analog Input TimerMnemonic for in-page Operation Inter PIN Description GND Absolute Maximum Ratings ~~x 125 P20-P23 -- .....--X..... ...Jr 108243 14P52 18243 GND 18243 Tes # pins= 60 mA-+- 8 mA/pin = 7.5= 1 2 3 4 5 6 7 8 9 10 11 12 Output Expander Timing 16,384·8IT ROM with Reset CE1CE2 Ready Symbol Parameter MIN MAX 8355/8355-2III ILO +- Al ~ Cl ~ 8355/8355·2 Input ModeOutput Mode PIN Configuration Block Diagram Directly Compatible with SOS5A CPU PROG/CE1 8755A8755AFUNCTIONAL PIN Definition SA Programming Module Cross Reference Module Name USE with UPPUPPI41 UPP UP2121 Symbol Parameter MIN MAX VIL 8755AComment Ready Hold Time Clock Specification for 8755A Prom Read, 1/0 Read and Write Timing Wait State Timing Ready =0 Voo Programming Voltage during Write To Eprom Specification ProgrammingITA =OC to 70C Vee =5V ± 5% Vss =OV Program Mode Timing Diagram Enable 8085A 8085A-28155-2 8156-2 8155/8156 PIN Functions Timer OUT8155/8156/8155-2/8156-2 Description 8156 Internal Registers Programming Command Register Reading the Status Register Control Input Mode Output Mode INPUT/OUTPUT SectionBFLowLow INTRLowHigh STB 8155/8156/8155-2/8156-2 Pca Timer Section Example Program WR AD ALE 8085A Minimum System ConfigurationInterval Timer Interrupt Levels Symbol Parameter MIN MAX Units Test Conditions VIL Symbol Parameter MIN MAX Units Read Cycle Write Cycle 8155/8156/8155-2/8156-2 WI\ J / j Basic Input Mode Basic Output Mode PIN Configuration Block Diagram PIN Names Truth Table for Power Down and Function Enable 8185/8185-2Operational Description Truth Table for Control and Data BUS PIN Status Absolute Maximum Ratings Comment 8185/8185-2 Page Page SINGLE-COMPONENT 8-BIT Microcomputer 0INTRODUCTION 8051 FamilyMACRO-VIEW of the 8051 Architecture 8051 CPU Architecture 21/0 Facilities ON-CHIP Peripheral Functions1Interrupt System 8031/8051/8751 3Timer/Event Counters 8031/8051/8751 8031/8051/8751 4Serial Communications ~=- J~~====~ ~DATA 8031/8051/8751 Circuit ground potential Psen XTAL1XTAL2 Family Development System and Software Support Symbol Parameter Min Typ Max Units Universal Prom Programmer Personality Card UPP-851Workshop Insite Library 12MHz Clock Data Memory Write Cycle Inter8031/8051/8751 8051 Instruction SET Summary Inter All mnemonics copyrlghted@ Intel CorporationPage Compatible MCS-48 Components PIN Configuration 1024 X 4 BIT Static RAM 2114A Family Unit Symbol ParameterAddress -..II-------------i--l Typical D.C. and .A.C. Characteristics Normauzed Access Time VS Supply Voltage 2316E 16K 2K 8 ROM 2316E Data ----=HIGHZ~--~~~~~~~~~~-OU-T~TV-ALIO~~~JlJJI PIN Configuration PIN Connection During Read or Program BB Power Supply 5V±5% 5Vt.5% -5V±5% -5V±10% Operating CharacteristicsFamily Nco and A.C.OPERATING Conditions During Read Address to Output Delay 2708·1 limits 2708·6Limits UnitsInput Capacitance VIN = OV Family Waveforms PIN Configuration Mode Selection PIN Names Programming CE = VIH. OE = VIL 2716 Cout 2716 Typical 16K Eprom System 2716 Device Operation Approved 8086·2 MPU .. .Zero Wait StateTwo Line Control Industry Standard Pinout . .. Jedec 8205 Ei==~ fEH2·E3 A13 --..,-H+-q E 8205Applications Eii-+-IH-+t-t r State Decoder Circuit Typical Characteristics \.. ~ ~TA = O·Cto + 75·C, Vee = 5V ± 5% MIN MAX Switching Characteristics CharactristicsConditions of Test Test Load Test Waveforms PIN Configuration Logic Diagram IT osGD ~s ------- + H DB ---------- -- +i Functional Description Il D+-+1 IE D Basic Schematic Symbols II. Gated Butter 3-StateGated Buffer DS2 , ------,----.J 8212 Here the 8212 is used as the status latch for an 8080A VI. Output Port With Hand-Shaking AD2 Bossa AD4 AD5 AD6 AD7~DI, Stbdo LOW Order CLR 8212 Output Currents 100mAInput Load Current, ACK, OS2, CR VF = A5V IOL = 15mA Ffi Ili Switching Characteristics Typ. Max CIN 051 MD Input Capacitance 9pF 12pF052. CK. ACK. DI1-Dls Input Capacitance 5pF DOs Output Capacitance 8pF TCI II,D SGS 821413214 Icex 8214/3214 Capacitances Inte Test Conditions Test Load Circuit ·BITPARALLEL Bidirectional BUS Driver 001 Bidirectional Driver Control aatlng OlEN, CS Waveforms Characteristics OUT O---T IFI IF2 IRI IR2 VIL VIH Voli VOL2 821618226 Applications of the 8216/8226 8282/8283 Octal Latch010 VCC PIN Definitions Operational Description PinD.scrlptlon VOL VOH TivovTshov Tehoz JJ\~ J/~~ 8282/8283 Intel Vee Ao-A7 Bo- B7 Characteristics for 8286/8287 Output Delay vs. Capacitance Jk~ Output Page Page Synchronous and Asynchronous Operation Synchronous 5·8 Bit Characters Features and Enhancements Iofl CapacitanceCapacitance pF Bus Parameters !Note Input Waveforms for AC Tests MIN MAX Unit Programmable Interval Timer General VIIi -.,--.,q System Interface Control Word Register Operational Description GeneralProgramming Control Word Format 825318253·5 Mode 2 Rate Generator =41 I---t--n --+ MSB 8253/8253-5LSB Read Operation Chart Mode Register for Latching CountRead Operations Reading While Counting Oe to 700 e Bus Parameters Note Input Waveforms for A.C. TestsRe.dCycle Write Timing 825318253·5 Clock and Gate Timing PIN Configuration 8255A Block Diagram Programmable Peripheral Interface 8255A18255A·5 8255A Functional Description8255A Basic Operation Face peripheral devices or structures PIN Configuration PIN Names 8255A18255A·5Group a and Group B Controls Ports A, B, and C 8255A Operational Description Mode SelectionSingle Bit Set/Reset Feature Operating Modes Interrupt Control Functions Mode 0 Port Definition Mode 0 Configurations 8255AJ8255A·5 PA7·pAo II I I I, I0 I0 I0 Input Control Signal Definition TPHIBF Input Buffer Full F/F Intr Interrupt Request Output Control Signal Definition 10 I ·IOMXlXlIntea Inte B Combinations of Mode Bidirectional Bus 1/0 Control Signal DefinitionOutput Operations Input Operations 8255.Al8255A·5 LtAOi ErXtJ I 0\ \, I, erXtJ I0\ Only Mode Definition Summary30AFN-00744A-14 Applications of the 8255A Printer Interface PC, r MSB Capacitance Read MIN. MAX Unit CIR TwB TRIT LtR1Bj SIB-Ii Programmable Interrupt Controller SP/EN 8259A Basic Functional Description 8259AInterrupts in Microcomputer Systems Interrupt Request Register IRR and IN·SERVICE Register ISR Priority ResolverInterrupt Mask Register IMR INT Interrupt 8259A 8259A Interface to Standard System BusCascade BUFFER/COMPARATOR Interrupt Sequence ~O ~ ~ Disable Function Programming the 8259AGeneral Input Operation Read Initialization Command Words 1 and 2 ICW1,ICW2 Initialization Command Word 3 ICW3 0 I 0 I 0 I 0 I 0 lID, liD, lIDo 8259A Operation Command Words OCWs Operation Control Word 1 OCW1Operation Control Word 2 OCW2 Operation Control Words Ocwi Ocwa R,-r-- I-i-Ioo r,-r,-r Operation Command Word FormatOJNTl Special Mask Mode Buffered ModeFully Nested Mode Special Fully Nested Mode Word enabled onto the data bus during m5 is Automatic END of Interrupt Aeoi ModeRotating Priority Mode B Rotation by Software Wol Priority Cell Simplified Logic Diagram Level Triggered ModeThis mode is programmed using bit 3 in ICW1 OH-++-+ 8272 Features 8272Registers CPU Interface Description 8272 Polling Feature Reset to the Interrupt signal IntJ Command SET Command Descriptions Read Data Write Data Transfer Capacity EN End of Cylinder Flag No No Data Flag Write Deleted Data Read Deleted DataRead a Track Readid Scan Commands Recalibrate Sense Interrupt StatusSpecify Sense Drive Status Status Registers BIT Name Symbol Description Usa DC Characteristics VIL CLK & WR CLK VIHCINI» VIN=OV ICY ~-----~---V Sel-I Timing Measurement Conditions LI3 Block Oiagram 8273, 8273·4, 8273·8 Brief Description of HDLC/SDLC Protocols 32XCLi Flag DET Programmable KEYBOARD/DISPLAY Interface RAM Principles of Operation 827918279-5Hardware Description 827918279·5 Software Operation End Interrupt/Error Mode Set Status WordData Read Data Write Interface Considerations Scanned Keyboard Mode, 2·Key Lockout ===~ General Block Diagram Applications IIL1 Symbol Test TYP MAXVIL2 Input Waveforms for A.C. Tests BUS Parameters 8279 Scan Timing Scan Waveforms Display Waveforms Gpib TALKER/LISTENER 8291 System Diagram 8291General Purpose Interface BUS Gpib General Description Acds PacsAcrs Ppas SH,AH,T,TE,L,LE,SR,RL,PP,C AH,CRemote Messages Received ATN SH,AH,T,TE,L,LE,PP,C DAB DAC Remote Messages Sent ATN DAB DACDAV END All Write Registers DontCare SPAS---SPAS Spasc Llcno LLO Lloc Interrupt Registers Menting this feature, with 80 and Bi enabied from ITO ILO I 0 I 0 I 0 I 0 Admi Aomoi Section on Parallel Poll Protocol Command Pass Through RegisterProvided for Auxiliary Mode Register Auxiliary Commands Internal Counter 2NFAuxiliary Register a Auxiliary Register B Reset Procedure Parallel Poll Protocol 8291 Using DMA 8291 to 8291A Software Compatibility Device Electrical Characteristics VOH-INTIlol Iloh TwA~ Timing Waveforms Gpib Timingsii Modified State Diagrams Figure A.1 State Diagrams next 101 TE,L,LE,C,CE Settling Time for Multiline Messages 21stResponse to ATN 200ns Interface Message Accept Time t Figure C-l -Wire Handshake Timing at Appendix C Figure C.2. Handshake Flowchart IIIL---,--11 ,--I 105 Gpib Controller 106 Ai1W Gpib Transceiver EOI BUS1BUS9 OATA1 Mode 0 PIN Description =OVGpib NDAC* I/O Ieee Gpib NrfoTIL Ndac Mode 1 PIN DescriptionMode 2 PIN Description Nrfd Ieee Mode 3 PIN Description R1L LIEN TiR1 Operating Characteristics 8293Absolute Maximum Ratings Capacitance Characteristics TA = O·Cto 70·C Vee= 5.0V ± 10% GND = OVTYP.· MAX ·118 Output Loading Test Circuits 8293 Waveforms 8294 8295 ·122 ====J 123 UPI·41A Features Enhancements Data Moves Signal DescriptionMnemonic Description Bytes Cycles 8041 Al8641 Al8741 a VIU IU1 Input and Output Waveforms for A.C. Tests Typical 8041/8741A CurrentRead OPERATION-DATA BUS Buffer Register Write OPERATION-DATA BUS Buffer Register WAVEFORMS-DMA CHARACTERISTICS-PORTCHARACTERISTICS-DMA PROGRAMMING, VERIFYING, and Erasing the 8741A Eprom VOO Vdol Timing Specification for ProgrammingSpecification for Programming Program 8041Al8641 Al8741A Support Products Page Microcomputer Development System Credit MODEL225 Functional Description 10-2 InterMODEL225 System Components Integral CRTPeripheral Interface Control Specifications Notavailable on bus 110V, 60 Hz 5.9 Amp 220V, 50 Hz 3.0 Amp9800556 9800292Page Intellec Prompt MCS·48 Microcomputer Design AID Intellec Prompt Features Single Component Compu.ter Prompt 48 Commands and Functions Intellec Prompt Intellec Prompt Functional Description MCS-48 Processors Cycle Time tCY = 2.5,..s Clock 6 MHz ± 0.1% User Interrupt causes an Interrupt only IfPrompt system Is running a user program Ordering Information MCS·48 IN·CIRCUIT Emulator ~ L · ICE·49 Memory Mapping GO from .START Till XDATA. Rslt Written ICE·49 ISIS·II EM1 Emulation Board EM1 EM1 Specifications DC Power Vcc5V ±5% Icc 300 mA maxOrdering Information MDS·EM1 EM2 Emulation Board 40·PIN Socket Configuration EM2 Block Diagram EM2ANO AN1 MDS-EM2 EM2UPP-1P3 Canadian Sales Offices September Canadian Distributors TAvnet Electronics McCormick Avenue Costa Mesa IntJ Bowers Avenue International Sales and Marketing Offices International DISTRIBUTORS/REPRESENTATIVES International Sales and Marketing Offices INTEL$ Marketing Offices Canadian Service Offices