Intel mcs-48 manual UPI·41A Features Enhancements

8041A/8641 Al8741A

UPI·41A™ FEATURES AND

ENHANCEMENTS

1.Two Data Bus Buffers, one for input and one for out· put. This allows a much cleaner Master/Slave pro· tocol.

INTERNAL

DATA BUS

INPUT

~DATA BUS(8)BUFFER

DO-D7 ' --------- '

OUTPUT

DATA

BUS

BUFFER

(8)

2.8 Bits of Status

If "EN FLAGS" has been executed, P25 becomes the IBF (Input Buffer Full) pin. A "1" written to P25 enables the IBF pin (the pin outputs the inverse of the IBF Status Bit). A "0" written to P25 disables the iBF pin (the pin remains low). iThis pin can be used to indicate that the UPI·41A is ready for data.

OBF (INTERRUPT REQUESn

fiiF (INTERRUPT REQUESn

DATA BUS BUFFER INTERRUPT CAPABILITY

FO I IBF OBF I

EN FLAGS Op Cod.: OF5H

ST4-ST7 are user definable status bits. These bits are defined by the "MOV STS, A" Single byte, Single cycle instruction. Bits 4-7 of the accumulator are moved to bits 4-7 of the status register. Bits 0-3 of the status register are not affected.

MOV STS. A Op Code: 90H

3.RD and WR are edge triggered. IBF, OBF, F1 and INT change internally after the trailing edge of RD or WR.

FLAGS AFFECTED

RO orW'R

4.P24 and P25 are port pins or Buffer Flag pins which can be used to interrupt a master processor. These pins default to port pins on Reset.

If the "EN FLAGS" instruction has been executed, P24 becomes the OBF (Output Buffer Full) pin. A "1" written to P24 enables the OBF pin (the pin outputs the OBF Status Bit). A "0" written to P24 disables the OBF pin (the pin remains low). This pin can be used to indicate that valid data is available from the UPI· 41A (in Output Data Bus Buffer).

5.P26 and P27 are port pins or DMA handshake pins for use with a DMA controller. These pins default to port pins on Reset.

If the "EN DMA" instruction has been executed, P26 becomes the DRQ (DMA ReQuest) pin. A "1" written to P26 causes a DMA request (ORO is activated). DRQ is deactivated by DACK'RD,DACK·WR,or execution of the "EN OM A" instruction.

If "EN DMA" has been executed, P27 becomes the DACK (DMA ACKnowledge) pin. This pin acts as a chip select input for the Data Bus Buffer registers during DMA transfers.

DRQ~	OROn
8041A!	8257
8741A DACK~
	DACK

OMA HANDSHAKE CAPABILITY

EN DMA Op Code: OESH

D,

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