Intel mcs-48 Eoi, BUS9, OATA10, Gno, Opta Optb OATA1 IFC, BUS1 IFC, BUS2 AEN, OATA3

Models: mcs-48

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8293

 

PIN DESCRIPTION

 

 

Symbo.

Symbol

110

Pin No.

 

Function

 

EOI

 

 

 

 

 

 

BUS1-

I/O

12,13,

These are the IEEE-488

bus

 

BUS9

 

1S·19,

interface

driver/rece!vers.

 

 

 

21,22 Using the mode select pins,

 

 

 

 

they can be configured .dlffer·

 

 

 

 

ently to allow direct connec·

 

 

 

 

tions between the 8291 GPIB

 

 

 

 

Talker/Listener and the

8292

 

 

 

 

GPIB Controller.

 

 

OATA1-

I/O

5·11,

These are the pins to be con·

ATN

 

OATA10

 

23-2S

nected to the 8291 and 8292 to

 

 

 

 

interface with the GPIB bus.

 

 

 

 

Their use is programmed by

 

 

 

 

the two mode select pins,

 

 

 

 

OPTA and OPTB. All these

oPTA

 

 

 

pins are TTL compatible.

 

T/R1

 

 

Transmit

receive 1; this

pin

OPTB

 

 

 

 

 

 

controls

the direction

for

 

 

 

 

NOAC, NAFO, OAV, and 0101-

 

 

 

 

0108. Input is TTL compatible.

Vee

T/R2

 

2

Transmit

receive 2; this

pin

 

 

 

controls the direction for EOL

 

 

 

 

Input is TTL compatible.

 

GNO

~[Q)W~OO©I§ OOOIF@rrulMl~lf'O@OO

110 Pin No;

Function

I/O 3 End or Identify; this pin indio cates the end of a multiple byte .transfer or, In conjunc· tion with ATN, addresses the device during a polling se· quence. It connects to the 8291 and is switched between transmit and receive by T/R2.

. This pin is TTL compatible.

04 Attention; this pin is used by the 8291 to monitor the GPIB' ATN control line. It specifies how data on the 010 lines is to be interpreted. This output is TTL compatible.

27These two pins are to control

I 26 the function of the 8293. A truth table of how this pro- grams the various modes is in Table 1.

P.S. 28 Positive power supply (SV

±10%).

P.S. 14,20 Circuit ground potential.

Table 1. 8293 Mode Selection Pin Mapping

 

 

 

 

 

 

 

IEEE Implementation Name

 

Pin Name

Pin No.

Mode 0

Mode 1

Mode 2

Mode 3

OPTA

27

0

1

0

1

OPTB

26

0

0

1

1

OATA1

S

IFC

0108

n=c

0108

BUS1

12

IFC'

0108'

IFC'

OIOS'

OATA2

6

AEN

0107

AEN

0107

BUS2

13

AEN'

0107'

AEN'

0107'

OATA3

7

NC

0106

EOl2

0106

BUS3

1S

EOI'

0106'

EOI'

0106'

OATA4

8

SAO

OIOS

SAO

0105

BUS4

16

SAO'

OIOS'

SAO'

OIOS'

OATAS

9

NAFO

0104

NAFO

0104

BUSS

17

NAFO'

0104'

NAFO'

0104'

OATA6

10

~

~

NOAC

0103

BUS6

18

NOAC'

0103'

NOAC'

0103'

OATA7

11

T/R101

NC

ATNI

ATNO

OATA8

23

T/R102

0102

ATNO

0102

BUS7

19

ATN'

0102'

ATN'

0102'

OATA9

24

G101

OAV

CIC

OAV

BUS8 .

21

G101'

OAV'

CLTH

OAV'

OATA10

2S

GI02

0101

IFCL

0101

BUS9

22

G102'

0101'

SYC

0101'

T/R1

1

T/R1

T/R1

TfR1

TlFh

T/R2

2

T/R2

NC

T/R2

IFCL

EOI

3

EOI

EOI

mr

EOI

ATN

4

ATN

Aiiil

Am'

ATN

'Note:These pins are the IEEE-488 bus non·lnvertlngdriver/receivers. They Include all the bus terminations required by the Standard and may be connected directly to the GPIB bus connector.

9-109

Page 424
Image 424
Intel mcs-48 Eoi, BUS9, OATA10, Gno, Opta Optb OATA1 IFC, BUS1 IFC, IFC Oios OATA2 AEN, BUS2 AEN, OATA3, OATA7