Intel mcs-48 manual Approved, 8086·2 MPU .. .Zero Wait State, Two Line Control

	2732A
32K (4K x 8) UV ERASABLE PROM
• 200ns (2732A·2) Maximum Access	• Pin Compatible to 2764 EPROM
Time ... HMOS*·E Technology
• Compatible to High Speed 8mHz	• Industry Standard Pinout . .. JEDEC
	Approved
8086·2 MPU .. .Zero WAIT State
• Two Line Control	• Low Standby Current . .. 35mA Max.

The Intel 2732A Is a 5Vonly, 32,384 bit ultraviolet erasable and electrically programmable read-only memory (EPROM). It Is pin compatl~le to Intel's450ns 2732. The standard 2732A'saccess time is 250ns with speed selection (2732A-2) available at 200ns. The access time is compatible to high performance microprocessors, such as the 8mHz 8086-2. In these systems, the 2732A allows the microprocessor to operate without the addition of WAIT states.

An Important 2732A feature is the separate output control, Output Enable (OE), from the Chip Enable control (CE). The OE control eliminates bus contention in multiple bus microprocessor systems. Intel'sApplication Note AP-72 describes the microprocessor system implementation of the OE and CEcontrols on Intel'sEPROMs. AP-72 Is available from Intel's Literature Department.

The 2732A has a standby mode which reduces the power dissipation without increasing access time. The maximum active current Is 150mA, while the maximum standby current is only 35mA, a 75% saving. The standby mode Is achieved by applying a TTL-high signal to the CE input.

The 2732A Is fabricated with HMOS*-E technology, Intel'shigh speed N-channel MOS Silicon Gate Technology.

	2764		MODE SELECTION
2732A	PIN CONFIGURATION			CE	OENpp
						Vcc	OUTPUTS
PIN CONFIGURATION v,,		'Vee	MODE	(18)	(20)	(24)	(9·11,13·17)
	An	POM	~			-+;5
	A1	N.CJ11	Read	VIL	VIL		DOUT
	As	A8	Standby	VIH	Don'tCare	+5	High Z
	A,	Ag	Program	VIL	Vpp	+5	DIN
	A,	A11
			Program Veri Iy			+5
	A3	OE		VIL	VIL		DOUT
	A.	A,O	Program Inhibit	VIH	Vpp	+5	High Z
	A,	CE
	AO
	00
	0,	0,		BLOCK DIAGRAM
	o.	0,
	GND	03
						DATA OUTPUTS
	('(Fortotal compatibility from		VCC~			00-07
	2732A provide a trace to pin 26		GNDO----
PIN NAMES
AO-Al1	ADDRESSES		AQ-A"			Y·GATING
CE	CHIP ENABLE		ADDRESS
			INPUTS
~	OUTPUT ENABLE		-		X	32.788·8IT
°o-Or	OUTPUTS			DECODER		CELL MATRIX

·HMOSIs a patented process of Intel Corporation.

8-17