8291

PIN DESCRIPTION

Symbol

I/O

Pin No.

Function

Do-D7

I/O

12-19

Data bus port, to be connected

 

 

 

to microprocessor data bus.

RSo-RS2

 

21-23

Register select inputs, to be con-

 

 

 

nected to three non-multiplexed

 

 

 

microprocessor address bus

 

 

 

lines. Select which of the 8 in-

 

 

 

ternal read (write) registers will

 

 

 

be read from (written into) with

 

 

 

the execution of RD (WR).

 

 

8

Chip select. When low, enables

 

 

 

reading from or writing into the

 

 

 

register selected by RSo-RS2.

 

 

9

Read strobe. When low, selected

 

 

 

register contents are read by the

 

 

 

CPU.

Symbol

I/O

Pin No.

Function

NRFD

I/O

37

Not ready for data; GPIB hand-

 

 

 

shake control line. Indicates the

 

 

 

condition of readiness of de-

 

 

 

vicels) connected to the bus to

 

 

 

accept data.

 

I/O

38

Not data accepted; GPIB hand-

 

 

 

shake control line. Indicates the

 

 

 

condition of acceptance of data

 

 

 

by the device(s) connected to

 

 

 

the bus.

 

 

26

Attention; GPIB command line.

 

 

 

Specifies how data on DIO lines

 

 

 

are to be interpreted.

 

 

24

Interface clear; GPIB command

 

 

 

line. Places the interface func-

 

 

 

tions in a known quiescent state.

10

o 11

DREQ o 6

DACK7

TRIG 0 5

Write strobe. When low, data is written into the selected register.

Interrupt request to the micro- processor, set high for request and cleared when the appropri- ate register is accessed by the CPU. May be software config- ured to be active low.

DMA request, normally low, set high to indicate byte output or byte input, in DMA mode; reset by DACK.

DMA acknowledge. When low, resets DREQ and selects data in/data out register for DMA data transfer (actual transfer done by RD/WR pulse).

Must be high if DMA is not used.

Trigger output, normally low; generates a triggering pulse with 1!,sec min. width in response to the GET bus command or Trigger auxiliary command.

 

o

27

Service request; GPIB command

 

 

 

line. Indicates the need for

 

 

 

attention and requests an inter-

 

 

 

ruption of the current sequence

 

 

 

of events on the GPIB.

 

 

25

Remote enable; GPIB command

 

 

 

line. Selects (in conjunction with

 

 

 

other messages I remote or local

 

 

 

control of the device.

 

I/O

39

End or identify; GPIB command

 

 

 

line. Indicates the end of a

 

 

 

multiple byte transfer sequence

 

 

 

or, in conjunction with ATN,

 

 

 

addresses the device during a

 

 

 

polling sequence.

T/R1

o

 

External transceivers control

 

 

 

line. Set high to indicate output

 

 

 

data/signals on the D101-D108

 

 

 

and DAV lines and input signals

 

 

 

on the NRFD and NDAC lines

 

 

 

(active source handshake I. Set

 

 

 

low to indicate input data/

 

 

 

signals on the D101·D108 and

CLOCK3

RESET4

I/O 36

External clock input, used only for T 1 delay generator. May be any speed in 1-8 MHz range.

Reset input. When high, forces the device into an "Idle" (initiali- zation) mode. The device will re- main at "Idle" until released by the microprocessor.

8-bit GPIB data port, used for bidirectional data byte transfer between 8291 and GPIB via non- inverting external line trans-

ceivers.

Data valid; GPIB handshake control line. Indicates the avail- ability and validity of infor- mation on the DIO lines.

 

 

 

DAV lines and output signals on

 

 

 

the NRFD and NDAC lines (ac-

 

 

 

tive acceptor handshake I.

T/R2

o

2

External transceivers control

 

 

 

line. Set high to indicate output

 

 

 

signals on the EOI line. Set low

 

 

 

to indicate expected input signal

 

 

 

on the EOI line during parallel

 

 

 

poll.

Vee

P.S.

40

Positive power supply (5V ±

 

 

 

10%).

GND

P.S.

20

Potential ground circuit.

Note: All signals on the 8291 pins are specified with positive logic. However, IEEE 488 specifies negative l~ on its 16 signal lines. Thus, the data is inverted once from 00-07 to 0101-0108 and non-inverting bus transceivers should be used.

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Image 398
Intel mcs-48 manual 8291