Intel mcs-48 manual Ei==~ fEH2·E3

8205

FUNCTIONAL DESCRIPTION

Decoder

The 8205 contains a one out of eight binary decoder. It ac· cepts a three bit binary code and by gating this input, creates an exclusive output that represents the value of the input code.

For example, if a binary code of 101 was present on the AO, A1 and A2 address input lines, and the device was enabled, an active low signal would appear on the 05 outputJine. Note that all of the other output pins are sitting at a logic high, thus the decoded output is said to be exclusive. The decoders outputs will follow the truth table shown below in the same manner for all other input variations.

Enable Gate

When using a decoder it is often necessary to gate the out· puts with timing or enabling signals so that the exclusive output of the decoded value is synchronous with the overall system.

Ao0.

A, 0;

A.z0,

0,

DECODER

0.

0;;

0;;

0,

.. ENABLE GATE

Ei:==~:) fEH2·E3)

E3

The 8205 has a built-in function for such gating. The three enable inputs (~, ~, E3) are ANDed together and create. a single enable signal for the decoder. The combination of both active "high" and active "low" device enable inputs provides the designer with a powerfully flexible gating func- tion to help reduce package count in his system.

Figure 1.

Enable Gate

ADDRESS

ENABLE

OUTPUTS

Ao

A,

A2

E, E2

E3

0

1

2

3 4

5

6

7

L

L

L

L

L

H L

H H H H H H H

H L

L

L

L

H H L

H

H H H H H

L

H L

L

L

H H H L

H H H H H

H H L

L

L

H H H H L H

H H H

L

L

H L

L

H H H H H L

H

H H

H L

H L

L

H H H H H H L

H H

L

H H L

L

H H H H H H H L

H

H H H L

L

H

H H H H H H H L

X X X L

L

L

H H H H H H H H

X X X H L

L

H H H H H H H H

X X X L

H L

H H H H H H H H

X X X H H L H H H H H H H H

X X X H L

H H H H H H H H H

X X X L

H H H H H H H H H H

X X X H H H H H H H H H H H

8-19 AFN-D0204B-02