Intel mcs-48 manual 8031/8051/8751, 3Timer/Event Counters

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Category	1.0.	Description	Comments
I/O Expander		8 Line I/O Expander	Low Cost I/O Expander
		(Shift Register)
Standard EPROMs	2758	1K x 8 450 ns Light	User programmable and
	2716-1	Erasable	erasable.
		2K x 8 350 ns Light
	2732	Erasable
		4K x 8 450 ns Light
	2732A	Erasable
		4K x 8 250 ns Light
		Erasable
Standard RAMs	2114A	1Kx4100nsRAM	Data memory can be
	2148	1K x 4 70 ns RAM	easily expanded using
	2142-2	1K x 4 200 ns RAM	standard NMOS RAMs.
Multiplexed Address/	8185A	1K x 8 300 ns RAM
Data RAMs
Standard I/O	8212	8-Bit I/O Port	Serves as Address Latch
	8282	8-Bit I/O Port	or I/O port.
	8283	8-Bit I/O Port
	8255A	Programmable	Three 8-bit programmable
	8251A	Peripheral Interface	I/O ports.
		Programmable Com-	Serial Communications
		munications Interface	Receiver/Transmitter.
Standard Peripherals	8205	1 of 8 Binary Decoder	MCS-80 and MCS-85
	8286	Bi-directional Bus Driver	peripheral devices are
	8287	Bi-directional Bus Driver	compatible with the 8051
		(Inverting)	allowing easy addition of
	8253A	Programmable Interval	specialized interfaces.
	8279	Timer	Future MCS-80/85
		Programmable	devices will also be
		Keyboard/Display	compatible.
	8291	Interface (128 Keys)
		GPIB Talker/Listener
	8292	GPIB Controller
Universal Peripheral	8041A	ROM Program Memory	User programmable to
Interfaces	8741A	EPROM Program	perform custom I/O and
		Memory	control functions.
Memories with	8155-2	256 x 8 330 ns RAM
on-chip I/O and	8355-2	2K x 8 330 ns ROM
Peripheral Functions.	8755-2	2K x 8 330 ns EPROM

Program Crystal

Or Data Frequency

Memory MHz (Max)

12

P9

P11

P9

P12

D	12
D	12
D	12
D	12
D	12
D	12
D	12
D	12
D	12
D	12
D	12
D	12
D	12
D	12
D	12
D	11.7
D/P	12/11.7
D/P	12/11.7

D12

P11.6

P11.6

Figure 2.3. 8051 Microcomputer Expansion Components

impedance state and Port 2 is returned to the state it had prior to the bus cycle. The 8051 generates the address, data and control signals needed by memory and I/O devices ina manner that minimizes the requirements placed on external program and data memories. At 12 MHz, the Program Memory cycle time is 500ns and the access times required from stable address and PSEN are approximately 320ns and 150ns respectively. The External Data Memory cycle time is 1J,Js and the access times required from stable address and from read (RD) or write (WR) command are approximately 600ns and 250ns respectively.

2.2.3Timer/Event Counters

The 8051 contains two 16-bitcountersformeasuring time intervals, measuring pulse widths, counting events and generating precise, periodic interrupt re- quests. Each can be programmed independently to operate similar toan 80488-bittimerwith divide by32 prescaler or as an 8-bit counter with divide by 32 pre- scaler (Mode 0), as a 16-bit time-interval or event counter (Mode 1), or as an 8-bittime-interval orevent counter with automatic reload upon overflow (Mode 2).

Additionally, counter 0 can be programmed to a mode that divides it into one 8-bit time-interval or

AFN-01462A~05

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