Intel mcs-48 manual Ai1W

8292

PIN DESCRIPTION

Symbol	I/O	Pin No.	Function
IFCL	I	1	IFC Received (latched) -				The 8292
			monitors the IFC Line (when not
			system controller)		throOgh			this
			pin.
X1, X2	I	2, 3	Inputs for a crystal, LC or an exter·
			nal timing signal to determine the
			internal oscillator frequency.
RESET	I	4	Used to initialize the chip to a
			known state during power on.
CS	I	6	Chip Select Input -		Used to select
			the 8292 from other devices on the
			common data bus.
RD	I	8	I/O write input which allows the
			master CPU to read from the 8292.
Ao	I	9	Address Line -	Used to select be-
			tween the data bus and the status
			register during	read		operations
			and to distinguish between data
			and commands written into the
			8292 during write operations.
WR	I	10	I/O read input which allows the
			master CPU to write to the 8292.
SYNC	0	11	8041 A instruction cycle				synchro-
			nization signal; it is an output
			clock with a frequency of
			XTAL ... 15.
Do-D7	I/O	12-19	8 bidirectional lines used for com-
			munication between			the central
			processor and the 8292'sdata bus
			buffers and status register.
Vss	P.S.	7, 20	Circuit ground potential.
SRO	I	21	Service Request -			One of		the
			IEEE control lines. Sampled by the
			8292 when it is controller in
			charge. If true, SPI interrupt to the
			master will be generated.
ATNI	I	22	Attention In - Used by the 8292 to
			monitor the GPIB ATN control
			line. It is used during the transfer
			control procedure.
IFC	I/O	23	Interface Clear -	One of the GPIB
			management lines, as defined by
			IEEE Std. 488-1978, places all de-
			vices in a known quiescent state.
SYC	I	24	System Controller -		Monitors the
			system controller switch.
CLTH	0	27	CLEAR LATCH Output -				Used to
			clear the IFCR latch after being
			recognized by the 8292. Usually
			low (except after hardware Reset),
			it will be pulsed high when IFCR is
			recognized by the 8292.
Ai1W	0	29	Attention Out -	Controls the ATN
			control line of the bus through ex-

ternal logic for tcs and tca pro- cedures. (ATN is a GPIB control line, as defined by IEEE Std. 488-1978.)

Symbol 1/0 Pin No_ Function

Vee P.S. 5,26,40 +5V supply input. ± 10%.

COUNT I 39 Count Input - When enabled by the proper command the internal counter will count external events through this pin. High to low tran- sition will increment the internal counter by one. The pin is sampled once per three internal instruction cycles (7.5I'sec sample period when using 6 MHz XTAL). It can be used for byte counting when con' nected to NDAC, or for block counting when connected to the

EOL

REN	0	38	The Remote Enable bus signal
			selects remote. or local control of
			the device on the bus. A GPIB bus
			management line, as defined by
			IEEE Std. 488-1978.
DAV	I/O	37	DAV Handshake Line -					Used dur-
			ing parallel poll to force the 8291
			to accept the parallel poll status
		...	bits. It is also used during the tcs
			procedure.
IBFI	0	36	Input Buffer Not Full -					Used to
			interrupt	the	central			processor
			while the input buffer of the 8292
			is empty. This feature is enabled
			and disabled by the interrupt
			mask register.
OBFI	0	35	Output Buffer Full -				Used as an
			interrupt to the central processor
			while the output buffer of the 8292
			is full. The feature can be enabled
			and disabled by the interrupt
			mask register.
EOl2	I/O	34	End Or Identify -			One of the GPIB
			management lines, as defined by
			IEEE Std. 488-1978. Used with ATN
			as Identify Message during paral-
			lel poll.
SPI	0	33	Special	Interrupt		-	Used		as an
			interrupt on events not initiated by
			the central processor.
TCI	0	32	Task Complete Interrupt -						Inter-
			rupt to the control processor used
			to indicate that the task requested
			was completed by the 8292 and
			the information requested is ready
			in the data bus buffer.
CIC	0	31	Controller In		Charge		-	Controls
			the SIR input of the SRO bus

transceiver. It can also be used to indicate that the 8292 is in charge of the GPIB bus.

9-107 00741C