Intel mcs-48 manual Expansion of Input/Output, EXPAND!!D MCS-48 System

EXPAND!!D MCS-48 SYSTEM

3.2.2Addressing ~Xt~rnal Data Memory External Data Memor~ Is ~~cessed with its own two-cycle move instructions MOVX A @R and MOVX @R, A which transfer 8 bits of data between the accumulator and the ex- ternal memory location addressed by the contents of one of the RAM Pointer Registers RO or R1. This allows 256 locations to be addressed in addition to the resident locations. Additional pages may be added by "bank switching" with extra output lines of the 8048.

3.2.3Examples of Data Memory Expansion

The accompanying figure shows how the 8048 can be expanded using standard 256 X 4 static RAMs such as the 2101-2 or its low power CMOS equivalent, the 5101. An 8212 serves as an address latch while each 4-bit half of BUS is connected directly to a bidirec-

tional 4-bit data bus of the memories. The WR output of the processor controls the Read/ Write input of the memories while the data bus output drivers of the memories are con- trolled by RD. The chip select lines of the memories are continuously enabled unless additional pages of RAM are required. Also shown is the expansion of data memory using the 8155 memory and I/O expanding device. Since the 8155 has an internal 8-bit address latch it can interface directly to the 8048 with- out the use of an external 8212 latch. The 8155 provides an additional 256 words of sta- tic data memory and also includes 22 I/O lines and a 14 bit timer. See the following sec- tion on I/O expansion and the 8155 data sheet for more details on these additional features.

3.3 Expansion of Input/Output

There are four possible modes of I/O expansion with the 8048: one using a special low cost expander, the 8243;

BUS	~------------	~s----------------------------			~
ALE	0S2	I/O 1·4	CS1		I/O 1-4	CS1
		A .~2111/2101 eI2			A .A 2111/2101C'S2
8048	1m 8212 gg~
		o 5101			o 7 5101
	MO	00	R/W		00	R/W
ROt--------------------		4----	~------------		~	~
~____~m~----------------------			~----------------
	sus K	8	ADo·7
	ALE "		ALE 8155	22	110
			268X8
				"	- y
	8048 WR		RAM
			WR		TIMER IN
	RD		iii)		TIMER OUT

PORT101M

3TEST

~INPUTS

18} 1/0

8048 INTERFACE TO 256 X 8 STANDARD MEMORIES

3·5