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Intel mcs-48 manual Specifications

Models: mcs-48

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interMODEL225

MULTIBUS™ Interface Capability

All Intellec Series 11/85 models implement the industry standard MULTIBUS protocol. The MULTIBUS protocol enables several bus masters, such as CPU and DMA devices, to share the bus

SPECIFICATIONS

Host Processor (lPC)

8085A-2 based, operating at 4.0 MHz. RAM - 64K on the CPU card

ROM - 4K (2K in monitor, 2K in boot/diagnostic) Bus - MULTIBUS™ bus, maximum transfer rate of 5 MHz

Clocks - Host processor, crystal controlled at

4.0MHz, bus clock, crystal controlled at 9.8304 MHz

I/O Interfaces

Two Serial I/O Channels, RS232C, at 110-9600 baud (asynchronous) or 150-56K baud (synchronous). Baud rates and serial format fully programmable using Intel 8251A USARTs. Serial Channel 1 addi- tionally provided with 20 mA current loop. Parallel I/O interfaces provided for paper tape punch, paper tape reader, printer, and UPP-103 Universal PROM Programmer.

and memory by operating at different priority levels. Resolution of bus exchanges is syn- chronized by a bus clock signal derived independently from processor clocks. Read/write transfers may take place at rates up to 5 MHz. The bus structure is suitable for use with any Intel microcomputer family.

Memory Access Time

RAM - 470 ns max

PROM - 540 ns max

Illtegral Floppy Disk Drive

Floppy Disk System Capacity - 250K bytes (formatted)

Floppy Disk System Transfer Rate - 160K bits/sec

Floppy Disk System Access Time - Track to Track: 10 ms max

Average Random Positioning: 260 ms

Rotational Speed: 360 rpm

Average Rotational Latency: 83 ms

Recording Mode: FM

Interrupts

8-level, maskable, nested priority interrupt net- work initiated from front panel or user selected devices.

Direct Memory Access (DMA)

Standard capability on MULTIBUS interface; implemented for user selected DMA devices through optional DMA module-maximum transfer rate ot5 MHz.

Physical Characteristics

CHASSIS

Width -17.37 in. (44.12 cm) Height -15.81 in. (40.16 cm) Depth -19.13 in. (48.59 cm) Weight - 731b. (33 kg)

KEYBOARD

Width -17.37 in. (44.12 cm) Height - 3.0 in. (7.62 cm) Depth - 9.0 in. (22.86 cm) Weight - 6 lb. (3 kg)

10-4	AFN-014248

Image 453

Intel mcs-48 manual Specifications

Contents

Page September MCS-48 Family of Single Chip Microcomputers UsersmanualMultibus BXPCredit PromptTable of Contents 8051/8751/8031 Microcomputer ChaptersEmulation Board 10-19 UPP-103 Universal Prom Programmer Emulation BoardInsite UsersLibrary Packing InformationPage Ntroduction Page Introduction to MCS-48 Introduction 5.0 and 10.0 J,Lsec Cycle Versions8021 is code compatible but not pin compatible with Introduction TilEprom Introduction Typical Computer System Function of a ComputerArchitecture of a CPU AccumulatorProgram Counter Jumps, Subroutines and the Stack Instruction Register and Decoder Three levels of subroutines may be ac- commodatedAddress Registers Arithmetic/Logic Unit ALUComputer Operations Control CircuitryTiming Instruction FetchMemory Write Input/OutputInterrupts To the next instructions When finished the processor continues onOur machine language program then becomes Step No. Hex Code Assembly Code MOV RO, #32Step Hex Code MOV R2, #05ADD A, # ALFA*BETA/2 Cpla ADD A, REGSUB R7 Developing An MCS-48 Based Product Hardware ConfigurationEducation Function DefinitionPrompt Production Intellec Development SystemPage Single Component MCS-4S S~stem Page Summary ArchitectureArithmetic Section ~BUS Location Single Component SystemInput/Output Single Component SystemSingle Component System Pointer R23+--1 R Jump ConditionsInterrupt Timing As an Event Counter As a TimerClock and Timing Circuits OscillatorALE --f---+--+ Instruction 111LOVI Power Down Mode BUS PCO·7RUN Stop Pin Description Designation 00-07Prog Number FunctionProgramming, Verifying and Erasing Eprom ResetSingle Component System Test and Debug ResetSingle Step Disabling Internal Program MemoryReading Internal Program Memory Following is a functional description of the major elements Program MemoryOscillator and Clock Timer/Event CounterQUASI-BIDIRECTIONAL Port Structure Input/Output Capabilities1 T1 Input High Current OutputsExpanded I/O Carry Flag Timer Overflow Flag Reset10 CPU Jump Test Condition Instructions AccumulatorFunctional Specifications Program MemoryData Memory Oscillator and Clock 15Timer/Event CounterPort 0 Comparator Inputs See the 8021 description, .8, for a com- plete explanationHigh Current Outputs Expanded 1/0Test and Interrupt Inputs 1-3 VAC Analog to Digital Converter Ill19 CPU Expanded Page Expansion of Program Memory SummaryInterrupt Routines Expanded MCS-48 SystemAI? Latch ROMLatch IOW Expansion of Data MemoryEXPAND!!D MCS-48 System Expansion of Input/OutputRead OO-Port #4 Write Port #5 10 or Port #6 Port #7 II AARD Display KeyboardExpansion Examples See Also Chapter Expanded MCS-48 SystemMulti-Chip MCS-48 Systems =====ll 8~~5 Memory Bank SwitchingPort Characteristics Control Signal SummaryBUS Port Operations Port 2 Operations000 Page Page Instruction SET Instruction SET Subroutines Instruction SET Instruction SET Summary 8021 RET Instruction SET SummarySymbols and Abbreviations Used DBFPSW ADD A,@R r Add Data Memory Contents to Accumulator ADD A,R r Add Register Contents to AccumulatorAddc A,R r Add Carry and Register Contents to Accumulator ADD A,#data Add Immediate Data to AccumulatorAddc A,#data Add Carry and Immediate Data to Accumulator ANL A,R r Logical and Accumulator With Register MaskANL A,@R r Logical and Accumulator With Memory Mask ANL A,#3+X/Y Andacc Contents with Value of EXP 3+X/Y ANL A,#data Logical and Accumulator With Immediate MaskAnld Pp,A Logical and Port 4-7 With Accumulator Mask With ACC Bits Andport 4 ContentsMOV RO,#50 Move 50DEC to Address INC RO Increment REG RET Return to Main ProgramCpla CPL Aacc Contents are COMPLE- Mented to 10010101111 Contents of the accumulator are cleared to zero11010 Flag 1 is cleared to zero F1-0 11 00 0 Flag 0 is cleared to zeroAC 7 4 3 0 o 1 0 ADD SIX to Bits 010100001 DA Aacc Adjusted to 00000001 with C SETADD SIX to Bits Overflow to CDEC Rr Decrement Register Not in 8021 Example Decrement contents of external data memory locationEN Tcnti Enable Timer/Counter Interrupt Not EN I Enable External InterruptEnto ClK Enable Clock Output Not in 8021,8022 A,Pp Input Port or Data to AccumulatorINC a Increment Accumulator INC Rr Increment RegisterINC @R r Increment Data Memory Location INS A,BUS Strobed Iput of BUS Data to Accumulator IputoPort 0 Data to Accumulator 8021, 8022 OnlyJBb address Jump If Accumulator Bit is Set Not in 8021 JC address Jump If Carry Is SetJMP address Direct Jump Within 2K Block JF1 address Jump If Flag 1 Is Set Not in 8021Jmpp @A Indirect Jump Within JNC address Jump If Carry Is Not SetJnto address Jump If Test 0 Is Low Not JNI address Jump If Interrupt Input is Low Not in 8021JNT1 address Jump If Test 1 Is Low JNZ address Jump If Accumulator Is Not ZeroIFTF=1 Jump to TimerroutineJump to Location 53 DEC Jump to CountroutineMaV A,R r Move Register Contents to Accumulator MaV A,PSW Move PSW Contents to Accumulator Not in 8021MaV A,@R r Move Data Memory Contents to Accumulator Mev A, #data Move Immediate Data to AccumulatorMev A,T Move Timer/Counter Contents to Accumulator MaV @Rr,A Move Accumulator Contents to Data Memory Movo A,Pp Move Port 4-7 Data to Accumulator Movo Pp,A Move Accumulator Data to PortMovp A,@A Move Current Page Data to Accumulator MOVP3 A,@A Move Page 3 Data to Accumulator Not in 8021,8022 Maxdm Movx A,@R1 Move Contents of LocationNot in 8021 Current page are Moved to ACCORL A,Rr Logical or Accumulator With Register Mask NOP The NOP InstructionORL A,@Rr Logical or Accumulator With Memory Mask ORL A,#data Logical OFJ Accumulator With Immediate Mask8021 Outl Pp,A Output Accumulator Data to Port 1 or Retr Return With PSW Restore Not in 8021 Example Assume carry is not set and accumulator contains Rrnc RR Anew ACC Contents areRrtc RRC a Carry is SET and ACC ContainsJMP $+20 SEL MBO Select Memory BankJump to Location 48 HEX10110101011 Stop Tcnt Stop Timer/Event-CounterJump to Routine Intif ACe BIT 3 is SET REG 7=8Strt T Start Timer Strt CNT Start Event CounterSwap a Swap Nibbles Within Accumulator XCH A,R r Exchange Accumulator-Register Contents XCH A,@R r Exchange Accumulator and Data Memory ContentsXchd A,@R r Exchange Accumulator and Data Memory 4-Bit Data XRL A,Rr Logical XOR Accumulator With Register Mask XRL A,@R1 Xoracc Contents with Mask LocationXRL A,@Rr Logical XOR Accumulator With Memory Mask XRL A,#data Logical XOR Accumulator With Immediate MaskAppli~ation Examples Page LC Oscillator Mode Crystal Oscillator ModeIntroduction Driving from External SourceApplication Examples Reset~~J Rvv-i T1 Multiple Interrupt Sources Ii6 Tf ~rServes as address latch Tt-2 A717&A3 ROM XtaliBoth 1/0 and RAM are addressed as data memory =!-39TOThis configuration is explained in section ResetF1L Expander Pinnumbers are Different for ~fd...LDB6 r ~1~Adding 8 Input Lines ·15 Application ExamplesAdding Output for KEYBOARD/DISPLAY Scanning RT T T T T JfLSubstitute a Application Examples Emulator Circuit DESCRIPTION-6 MHZInterface to Drum Printer Timer RAMII Keyboard Display Microwave Oven Controller Double Subtract Double ADDDouble Load Double StoreDouble Left Logical Shift Application Examples Double ExchangeDouble Right Logical Shift Double Right Arithmetic ShiftInterrupt Handling Application Examples Binary MultiplyR1,A Application Examples Byte Processing SystemCPL Subtract Second from First INC 2sCOMPLEMENT and ADDSee AP-49 8 MULTIPLY-ASSEMBLED by MCS-48 Macro AssemblerIIn ·1 16 x 8 DIVIDE-ASSEMBLED by MCS-48 Macro ASS.E.MBLERSEE AP-49 APP\,JCATION Examples16 x 8 DIVIDE-ASSEMBLED by MCS-48 Macro Assembler see AP-49 Page MCS-4STMComponent Page IIH!T Hmos Single Component 8-BIT MicrocomputerAddress latch enable. This Used to enable data ontoSignal occurs once during Program store enable. ThisS04SH/S04SH-1 /S035HL-1/S035H L-1 Absolute Maximum RATINGS· Inter 8048H/8048H-1/8035HL/8035HL.1BUS Timing AS a Function of TCY Port 2 TimingWaveforms S04SH/S04SH-1/S035HL/S035HL-1Read From External Data Memory 8035HLJ3 Xtal Z 8048H/8048H·1/8035HL/8035HL·1Rll PIN Configuration Logic Symbol Block DiagramBlock Diagram PIN Configuration Logic SymbolPIN Description 8048/8035L/8748/8748-6/8748-8/8035/8035-8AFN-Q1354A-03 Input High Voltage X1, X2, RESEi All Except XTAL1, XTAL2, ResetVOL =2.0 mA Output Low Voltage 10L = 1.8 mA===i---h·1 Characteristics Port 2 Timing LC Oscillator Mode Crystal Oscillator ModeDriving from External Source PROGRAMMING, VERIFYING, and Erasing the 8748 EpromTA = 2SOC ± SoC, Vee =SV ± S%, Voo = 2SV ± Waveforms for Programming Verify .I.~---PROGRAMPROMPT-48 Microcomputer Design Aid, or Intel Corporation 108048/8748/8035L 108048/8748/8035L IDS0481S7481S035L Operating CharacteristicsAbsolute Maximum RATINGS· BUSP1, P2BUS, P1, P2260 TAD Address Setup to Data TAW Address Setup to WRTOR Data Hold PSEN, RD to DataTop Port Control Setup Before Failing Edge of Prog CharacteristicsTpL Port 2 I/O Data Setup TA= -40·Cto +85·C, Vcc=5V ±10%, Vss=OVReset Crystal Oscillator Mode Driving from External Source+-----t XTALl ProgTA = 25C ± 5C, Vee = 5V ± 5%, Vee = 25V ± TA =25C ± 5C, Vee =5V ± 5%, Vee =25V ±PROMPT-48 Microcomputer Design Aid. or Waveforms for ProgrammingInter Lcoscillator Mode VooProgramming Verification Unit Test Conditions IPHVoo Program Voltage High Level 24.0 2S.0 EA Program or Verify Voltage High Level 21.5 24.5 8748M8048/M8748/M8035L EA 5M8048/M8748/M8035L Prog Pin #TpL Port 2 1/0 Data Setup Tcp Port Control Setup Before FallingTpo Output Data Hold Time Tpp Prog Pulae Width TLP Port 2 1/0 Data Hold 120ALE JI ~----r---I L CharacteristicsBUS, P1, P2 AN D Operati NG CharacteristicsInter 80411803118031 8049/8039 Symbol Parameter Min Max Unit Operating CharacteristicsALE JIL --------..1.--1----L Mask Programmable ROM External ROM or Eprom MHz Operation 18049/8039INr Til IntJ18049/8039BUS, RD, WR, PSEN, ALE VIH1VOL2 BUS, RD, WR, PSEN, ALE VOH1Waveforms TAFC--1 I~OATING-I t=t orPort 2 1/0 Data Setup 300 Output Data Setup Time 230TA = -400C to +850 C, Vee = Voo = +5V ±10%, Vss = OV Unit Conditions NoteXT AL1 Crystal Oscillator Mode LC Oscillator Mode8021 PIN Configuration Logic Symbol Block DiagramV1Hl Input High Voltage Xtal 1 & 2, T1 OC to 70CVIH10% Input high voltage all except Xtal 1 T1, RESElXTAL2 ALE8022 Prog POO-P07 Reset AvssVTH Varef ANO,AN1 ALE XtalFzx 8022Port 2 Timing IpAL---ooj·1Analog Input Timing AID Converter CharacteristicsAnalog Input 0, Analog Input Timer Mnemonic for in-page OperationCNT Inter GND PIN DescriptionAbsolute Maximum Ratings ~~x 125 P20-P23 -- .....--X..... ...Jr 14P52 108243GND 1824318243 Tes 1 2 3 4 5 6 7 8 9 10 11 12 # pins= 60 mA-+- 8 mA/pin = 7.5=Output Expander Timing 16,384·8IT ROM with CE1 ResetCE2 Ready8355/8355-2 Symbol Parameter MIN MAXIII ILOCl ~ +- Al ~Input Mode Output Mode8355/8355·2 Directly Compatible with SOS5A CPU PIN Configuration Block Diagram8755A 8755AFUNCTIONAL PIN DefinitionPROG/CE1 UPP SA Programming Module Cross Reference Module Name USE withUPPI41 UPP UP21218755A Symbol Parameter MIN MAX VILComment Ready Hold TimeProm Read, 1/0 Read and Write Timing Clock Specification for 8755AWait State Timing Ready =0 Specification Programming ITA =OC to 70C Vee =5V ± 5% Vss =OVVoo Programming Voltage during Write To Eprom Program Mode Timing Diagram 8085A 8085A-2 Enable8155-2 8156-2Timer OUT 8155/8156/8155-2/8156-28155/8156 PIN Functions 8156 Internal Registers DescriptionReading the Status Register Programming Command RegisterINPUT/OUTPUT Section Control Input Mode Output ModeBFLowLow INTRLowHigh STBPca 8155/8156/8155-2/8156-2Timer Section Example Program 8085A Minimum System Configuration Interval Timer Interrupt LevelsWR AD ALE Symbol Parameter MIN MAX Units Test Conditions VIL MIN MAX Units Symbol ParameterWrite Cycle Read CycleWI\ J / j 8155/8156/8155-2/8156-2Basic Output Mode Basic Input ModePIN Names PIN Configuration Block Diagram8185/8185-2 Truth Table for Power Down and Function EnableOperational Description Truth Table for Control and Data BUS PIN StatusComment Absolute Maximum Ratings8185/8185-2 Page Page SINGLE-COMPONENT 8-BIT Microcomputer 8051 Family 0INTRODUCTIONMACRO-VIEW of the 8051 Architecture 8051 CPU ArchitectureON-CHIP Peripheral Functions 1Interrupt System21/0 Facilities 8031/8051/8751 8031/8051/8751 3Timer/Event Counters4Serial Communications 8031/8051/8751~=- J~~====~ ~DATA Circuit ground potential 8031/8051/8751XTAL1 PsenXTAL2 Family Development System and Software SupportUniversal Prom Programmer Personality Card UPP-851 Symbol Parameter Min Typ Max UnitsWorkshop Insite Library12MHz Clock Data Memory Write Cycle 8051 Instruction SET Summary Inter8031/8051/8751All mnemonics copyrlghted@ Intel Corporation InterPage Compatible MCS-48 Components 1024 X 4 BIT Static RAM PIN Configuration2114A Family Symbol Parameter Address -..II-------------i--lUnit Normauzed Access Time VS Supply Voltage Typical D.C. and .A.C. Characteristics2316E 16K 2K 8 ROM 2316E Data ----=HIGHZ~--~~~~~~~~~~-OU-T~TV-ALIO~~~JlJJI PIN Connection During Read or Program PIN ConfigurationOperating Characteristics BB Power Supply 5V±5% 5Vt.5% -5V±5% -5V±10%Family Nco and A.C.OPERATING Conditions During Read2708·1 limits 2708·6Limits Units Address to Output DelayInput Capacitance VIN = OVWaveforms FamilyPIN Names PIN Configuration Mode SelectionCE = VIH. OE = VIL ProgrammingCout 2716Typical 16K Eprom System 2716Device Operation 27168086·2 MPU .. .Zero Wait State ApprovedTwo Line Control Industry Standard Pinout . .. Jedec8205 Ei==~ fEH2·E3 8205 A13 --..,-H+-q EApplications Eii-+-IH-+t-t rState Decoder Circuit \.. ~ ~ Typical CharacteristicsTA = O·Cto + 75·C, Vee = 5V ± 5% MIN MAXCharactristics Switching CharacteristicsConditions of Test Test Load Test WaveformsIT os PIN Configuration Logic DiagramGD ~s ------- + H DB ---------- -- +iIl D Functional Description+-+1 IE DII. Gated Butter 3-State Basic Schematic SymbolsGated Buffer DS2 , ------,----.J8212 VI. Output Port With Hand-Shaking Here the 8212 is used as the status latch for an 8080ABossa AD4 AD5 AD6 AD7 AD2~DI, Stbdo LOW Order CLROutput Currents 100mA 8212Input Load Current, ACK, OS2, CR VF = A5V IOL = 15mAIli FfiTyp. Max CIN 051 MD Input Capacitance 9pF 12pF Switching Characteristics052. CK. ACK. DI1-Dls Input Capacitance 5pF DOs Output Capacitance 8pFTCI SGS II,DIcex 821413214Capacitances 8214/3214Test Conditions Test Load Circuit Inte001 ·BITPARALLEL Bidirectional BUS DriverControl aatlng OlEN, CS Bidirectional DriverOUT O---T Waveforms CharacteristicsVoli VOL2 IFI IF2 IRI IR2 VIL VIHApplications of the 8216/8226 821618226Octal Latch 8282/8283010 VCCPinD.scrlptlon PIN Definitions Operational DescriptionTivov VOL VOHTshov TehozJJ\~ J/~~ 8282/8283 Vee IntelBo- B7 Ao-A7Characteristics for 8286/8287 Jk~ Output Delay vs. CapacitanceOutput Page Page Synchronous 5·8 Bit Characters Synchronous and Asynchronous OperationFeatures and Enhancements Capacitance Capacitance pFIofl Input Waveforms for AC Tests Bus Parameters !NoteMIN MAX Unit Programmable Interval Timer VIIi -.,--.,q GeneralControl Word Register System InterfaceGeneral Operational DescriptionProgramming Control Word Format825318253·5 =41 I---t--n --+ Mode 2 Rate Generator8253/8253-5 LSBMSB Mode Register for Latching Count Read Operation ChartRead Operations Reading While CountingOe to 700 e Input Waveforms for A.C. Tests Bus Parameters NoteRe.dCycle Write TimingClock and Gate Timing 825318253·5Programmable Peripheral Interface PIN Configuration 8255A Block Diagram8255A Functional Description 8255A18255A·58255A Basic Operation Face peripheral devices or structures8255A18255A·5 PIN Configuration PIN NamesGroup a and Group B Controls Ports A, B, and CMode Selection Single Bit Set/Reset Feature8255A Operational Description Interrupt Control Functions Operating ModesMode 0 Configurations Mode 0 Port DefinitionPA7·pAo 8255AJ8255A·5II I I I, I0 I0 I0 TPH Input Control Signal DefinitionIBF Input Buffer Full F/F Intr Interrupt Request10 I ·IOMXlXl Output Control Signal DefinitionIntea Inte BBidirectional Bus 1/0 Control Signal Definition Combinations of ModeOutput Operations Input OperationsLtAOi 8255.Al8255A·5\, I, erXtJ I0\ ErXtJ I 0\Mode Definition Summary 30AFN-00744A-14Only Printer Interface Applications of the 8255AMSB PC, rCapacitance MIN. MAX Unit ReadCIR TRIT LtR1Bj TwBSIB-Ii SP/EN Programmable Interrupt Controller8259A Interrupts in Microcomputer Systems8259A Basic Functional Description Priority Resolver Interrupt Request Register IRR and IN·SERVICE Register ISRInterrupt Mask Register IMR INT Interrupt8259A Interface to Standard System Bus 8259ACascade BUFFER/COMPARATOR Interrupt Sequence~O ~ ~ Programming the 8259A Disable FunctionGeneral Input Operation ReadInitialization Command Word 3 ICW3 Initialization Command Words 1 and 2 ICW1,ICW28259A 0 I 0 I 0 I 0 I 0 lID, liD, lIDoOperation Control Word 1 OCW1 Operation Command Words OCWsOperation Control Word 2 OCW2 Operation Control Words Ocwi OcwaOperation Command Word Format OJNTlR,-r-- I-i-Ioo r,-r,-r Buffered Mode Special Mask ModeFully Nested Mode Special Fully Nested ModeAutomatic END of Interrupt Aeoi Mode Word enabled onto the data bus during m5 isRotating Priority Mode B Rotation by Software WolLevel Triggered Mode Priority Cell Simplified Logic DiagramThis mode is programmed using bit 3 in ICW1 OH-++-+8272 8272 FeaturesRegisters CPU Interface Description8272 Reset to the Interrupt signal Polling FeatureIntJ Command SET Read Data Command DescriptionsTransfer Capacity EN End of Cylinder Flag No No Data Flag Write DataRead Deleted Data Write Deleted DataRead a Track ReadidScan Commands Sense Interrupt Status RecalibrateSpecify Sense Drive StatusUsa Status Registers BIT Name Symbol DescriptionVIL CLK & WR CLK VIH DC CharacteristicsCINI» VIN=OVICY ~-----~---V Timing Measurement Conditions Sel-IBlock Oiagram LI3Brief Description of HDLC/SDLC Protocols 8273, 8273·4, 8273·8Flag DET 32XCLiRAM Programmable KEYBOARD/DISPLAY Interface827918279-5 Hardware DescriptionPrinciples of Operation 827918279·5 Software Operation Status Word End Interrupt/Error Mode SetData Read Data WriteScanned Keyboard Mode, 2·Key Lockout Interface Considerations===~ Applications General Block DiagramSymbol Test TYP MAX VIL2IIL1 BUS Parameters Input Waveforms for A.C. Tests8279 Display Waveforms Scan Timing Scan WaveformsGpib TALKER/LISTENER 8291 8291 System DiagramGeneral Purpose Interface BUS Gpib General DescriptionPacs AcdsAcrs PpasAH,C SH,AH,T,TE,L,LE,SR,RL,PP,CRemote Messages Received ATN SH,AH,T,TE,L,LE,PP,C DAB DACDAC Remote Messages Sent ATN DABDAV ENDDontCare All Write RegistersInterrupt Registers SPAS---SPAS Spasc Llcno LLO LlocMenting this feature, with 80 and Bi enabied from ITO ILO I 0 I 0 I 0 I 0 Admi Aomoi Command Pass Through Register Provided forSection on Parallel Poll Protocol Auxiliary Commands Auxiliary Mode Register2NF Internal CounterAuxiliary Register a Auxiliary Register BParallel Poll Protocol Reset Procedure8291 Using DMA 8291 to 8291A Software Compatibility VOH-INT Device Electrical CharacteristicsIlol IlohTiming Waveforms TwA~Gpib Timingsii Figure A.1 State Diagrams next Modified State Diagrams101 Settling Time for Multiline Messages 21st Response to ATN 200ns Interface Message Accept Time tTE,L,LE,C,CE Appendix C Figure C-l -Wire Handshake Timing atFigure C.2. Handshake Flowchart 105 IIIL---,--11 ,--I106 Gpib ControllerAi1W Gpib Transceiver BUS1 EOIBUS9 OATA1=OV Mode 0 PIN DescriptionGpib NDAC* I/ONrfo TILIeee Gpib Mode 1 PIN Description Mode 2 PIN DescriptionNdac Ieee NrfdMode 3 PIN Description LIEN R1LTiR1 8293 Operating CharacteristicsAbsolute Maximum Ratings CapacitanceTA = O·Cto 70·C Vee= 5.0V ± 10% GND = OV CharacteristicsTYP.· MAX ·118Output Loading Test Circuits Waveforms 82938294 ·122 8295123 ====JUPI·41A Features Enhancements Signal Description Mnemonic Description Bytes CyclesData Moves 8041 Al8641 Al8741 a IU1 VIUTypical 8041/8741A Current Input and Output Waveforms for A.C. TestsRead OPERATION-DATA BUS Buffer Register Write OPERATION-DATA BUS Buffer RegisterCHARACTERISTICS-PORT CHARACTERISTICS-DMAWAVEFORMS-DMA VOO PROGRAMMING, VERIFYING, and Erasing the 8741A EpromTiming Specification for Programming Specification for ProgrammingVdol 8041Al8641 Al8741A ProgramSupport Products Page Credit Microcomputer Development System10-2 MODEL225 Functional DescriptionIntegral CRT InterMODEL225 System ComponentsPeripheral Interface ControlSpecifications 110V, 60 Hz 5.9 Amp 220V, 50 Hz 3.0 Amp Notavailable on bus9800556 9800292Page Intellec Prompt MCS·48 Microcomputer Design AID Single Component Compu.ter Intellec Prompt FeaturesIntellec Prompt Prompt 48 Commands and FunctionsMCS-48 Processors Intellec Prompt Functional DescriptionUser Interrupt causes an Interrupt only If Prompt system Is running a user programCycle Time tCY = 2.5,..s Clock 6 MHz ± 0.1% Ordering Information MCS·48 IN·CIRCUIT Emulator ICE·49 ~ L ·GO from .START Till XDATA. Rslt Written Memory MappingISIS·II ICE·49EM1 Emulation Board EM1 DC Power Vcc5V ±5% Icc 300 mA max EM1 SpecificationsOrdering Information MDS·EM1EM2 Emulation Board EM2 40·PIN Socket Configuration EM2 Block DiagramANO AN1EM2 UPP-1P3MDS-EM2 September Canadian Sales OfficesTAvnet Electronics McCormick Avenue Costa Mesa Canadian DistributorsIntJ International DISTRIBUTORS/REPRESENTATIVES Bowers Avenue International Sales and Marketing OfficesINTEL$ Marketing Offices International Sales and Marketing OfficesCanadian Service Offices