Intel mcs-48 manual Using DMA 8291 to 8291A Software Compatibility

8291

Using DMA 8291 to 8291A Software Compatibility

The 8291 may be connected to the Intel<l> 8237 or 8257 DMA Controllers for DMA operation. The DREO pin of the 8291 requests a DMA byte transfer from the 8237. It Is set by BO or BI flip flops, enabled by the DMAO and DMAI bits In the Interrupt Enable 2 Register. (After read· ing, the INT1 register BO and BI interrupts will be cleared but not BO and BI In DREO equation.)

The DACK pin Is driven by the 8237 in response to the DMA request. When DACK is true (active low) it sets CS= RSO= RS1 = RS2=0 such that the m; and WR signals sent by the 8237 refer to the Data In and Data Out Regis· ters. Also, the DMA request line is reset by DACK.

DMA input sequence:

1.A data byte is accepted from the GPIB by the 8291.

2.A BI interrupt is generated and DREO is set.

3.DACK is asserted by the 8237 and DREO is reset.

4.RD is driven bv the 8237 and the contents of the Data In Register are transferred to MCS™ bus.

5.The 8291 sends RFD true on the GPIB and proceeds with the Acceptor Handshake protocol.

DMA output sequence:

1.A BO interrupt is generated (indicating that th.e Data Out Register is empty) and DREO is asserted.

2.DACK Is asserted by the 8237 and DREO is reset.

3.ii'm Is driven by the 8237 and a byte Is transferred from the MCS bus Into the Data Out Register.

4.The 8291 sends DAV true on the GPIB and proceeds with the Source Handshake protocol.

It should be noted that each time the device is addressed, the Address Status Register should be read, and the 8237 should be initialized accordingly. (Refer to the 8237 or 8257 Data Sheets.)

System Configuration

Microprocessor Bus Connection

The 8291 is 8080, 8048, 8085, 8088, and 8086 compatible. The three address pins (RSo. RS1, RS2) should be connected to the non-mUltiplexed address bus (for example: As. Ag, A10). In case of 8080, any address lines may be used.

External Transceivers Connection

The 8293 GPIB Transceiver interfaces the 8291 directly to the IEEE·488bus. The 8291 and two 8293'scan be con· figured as a talker/listener (see Figure 2) or as with the 8292 as a talker/listener/controller (see Figure 3). Ab· solutely no active or passive external components are re- quired to comply with the complete IEEE·488 electrical specification.

Intel will be improving the 8291 by manufacturing an 8291A. To maintain software compatibility between the 8291 and the 8291A, the following precautions should be taken In the 8291 software:

1.BO interrupt indicates that the 8291 is ready to talk and needs a byte to output via the source handshake. The software should ensure that BO is true before writing a byte to the Data Out Register (even for the first byte after being addressed to talk).

2.SPASC interrupt should not be used during a Serial Poll sequence to determine when the Status Byte has been issued after a Service Request.

Before setting rsv, SPAS in.register 2 should be zero. After setting rsv, the processor should poll the SROS bit in register 3, and when it is clear the Status Byte has been Issued. The processor should then write an rsv local message clearing rsv.

The definition of the SPASC interrupt will change in the 8291 A. SPASC (Serial Poll Active State Change) in the 8291 is set by a transition into or out of SPAS. SPASC (Serial Poll Active State Complete) in the 8291A will be set only by the actual transfer of a Status Byte (APRSxSTRSxSPAS).

3.The 8291 rtl local message is set by the rtl Auxiliary Command and is cleared automatically by the 8291. The 8291A will have a Set rtl Auxiliary Command (1101) and a Clear rtl Auxiliary Command (0101). Thus, the 8291 programmer should write a Set rtl Auxiliary Command followed by a Clear rtl Auxiliary Command which will have the effect of writing two consecutive rtl commands.

4.User'ssoftware can distinguish between the 8291 and the 8291A as follows:

a)pon (OOH to register 5)

b)RESET (02H to register 5)

c)Read Interrupt Status Register 1. If BO interrupt is set, the device is the 8291. If BO is clear, It is the 8291A.

This can be used to set a.11ag in the user'ssoftware which will permit special routines to be executed for each device. It could be Included as part of a normal initialization procedure as the first step after a chip reset.

The 8291A will be a significant improvement over the 8291. Users should plan to convert to this product when It is available.

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