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Intel mcs-48 manual 8294

Models: mcs-48

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8294

DATA ENCRYPTION UNIT

•Certified by National Bureau of Standards

•SO Byte/Sec Data Conversion Rate

•64·Blt Data Encryption Using 56· Bit

Key

•DMA Interface

•3 Interrupt Outputs to Aid In Loading and Unloading Data

DESCRIPTION

•7·Blt User Output Port

•Single 5V ::t 10% Power Supply

•Peripheral to MCS·S6™, MCS·S5™, MC5-S0™ and MCS·48™ Processors

•Implements Federal Information Processing Data Encryption Standard

•Encrypt and Decrypt Modes Available

The Intell!> 8294 Data Encryption Unit (DEU) is a microprocessor peripheral device designed to encrypt and decrypt 64·bitblocks of data using the algorithm specified in the Federal Information Processing Data Encryption Standard. The DEU operates on 64·bittext words using a 56·bituser·specifledkey to produce 64·bltcipher words. The operation is reversible: if the cipher word Is operated upon, the original text word is produced. The algorithm itself is perma· nently contained in the 8294; however, the 56·blt key is user·defined and may be changed at any time.

The 56·bit key and 64·bltmessage data are transferred to and from the 8294 in 8·bitbytes by way of the system data bus. A DMA interface and three interrupt outputs are available to minimize software overhead associated with data transfer. Also, by using the DMA interface two or more DEUs may be operated In parallel to achieve effective system conversion rates which are virtually any multiple of 80 bytes/second. The 8294 also has a 7·bitTTL compatible output port for user·specified functions.

Because the 8294 implements the NBS encryption algorithm it can be used in a variety of Electronic Funds Transfer applications as well as other electronic banking and data handling applications where data must be encrypted.

	PIN
CONFIGURATION			BLOCK DIAGRAM
		Vee	DATA
		Ne	DATA
		Ne	BUS
		!lACK	BUS
		!lACK
		ORO
		SRO
		DAV
		Ne
		P6	Ac
		PS	Ac
		P'	SRQ
		P3	DAV
		P2	teMP
01		PI	po'p,
02		PO	RESET
03		VDD	RESET
03		VDD	SYNC
D4		Ne	SYNC
D4		Ne
OS		CCMP	X,
06		Ne	X,
07		Ne	x,
GND		NC
			+5V -

	POWER --	INTERNAL
		BUS
	OND --

9-121

oo230B

Image 436

Intel mcs-48 manual 8294

Contents

Page MCS-48 Family of Single Chip Microcomputers Usersmanual SeptemberBXP MultibusCredit PromptTable of Contents Chapters 8051/8751/8031 MicrocomputerEmulation Board Emulation Board 10-19 UPP-103 Universal Prom ProgrammerInsite UsersLibrary Packing InformationPage Ntroduction Page Introduction to MCS-48 5.0 and 10.0 J,Lsec Cycle Versions Introduction8021 is code compatible but not pin compatible with Til IntroductionEprom Introduction Function of a Computer Typical Computer SystemArchitecture of a CPU AccumulatorProgram Counter Jumps, Subroutines and the Stack Three levels of subroutines may be ac- commodated Instruction Register and DecoderAddress Registers Arithmetic/Logic Unit ALUControl Circuitry Computer OperationsTiming Instruction FetchInput/Output Memory WriteInterrupts When finished the processor continues on To the next instructionsStep No. Hex Code Assembly Code MOV RO, #32 Our machine language program then becomesStep Hex Code MOV R2, #05Cpla ADD A, REG ADD A, # ALFA*BETA/2SUB R7 Hardware Configuration Developing An MCS-48 Based ProductEducation Function DefinitionPrompt Intellec Development System ProductionPage Single Component MCS-4S S~stem Page Architecture SummaryArithmetic Section ~BUS Single Component System LocationSingle Component System Input/OutputSingle Component System R23 PointerJump Conditions +--1 RInterrupt Timing As a Timer As an Event CounterClock and Timing Circuits OscillatorALE --f---+--+ 111 InstructionLOVI BUS PCO·7 Power Down ModeRUN Stop Pin Description 00-07 DesignationProg Number FunctionReset Programming, Verifying and Erasing EpromSingle Component System Reset Test and DebugSingle Step Disabling Internal Program MemoryReading Internal Program Memory Program Memory Following is a functional description of the major elementsTimer/Event Counter Oscillator and ClockInput/Output Capabilities QUASI-BIDIRECTIONAL Port StructureHigh Current Outputs 1 T1 InputExpanded I/O Reset Carry Flag Timer Overflow Flag10 CPU Jump Test Condition Instructions AccumulatorProgram Memory Functional SpecificationsData Memory 15Timer/Event Counter Oscillator and ClockPort 0 Comparator Inputs See the 8021 description, .8, for a com- plete explanationExpanded 1/0 High Current OutputsTest and Interrupt Inputs 1-3 VAC Ill Analog to Digital Converter19 CPU Expanded Page Summary Expansion of Program MemoryExpanded MCS-48 System Interrupt RoutinesROM AI? LatchLatch Expansion of Data Memory IOWExpansion of Input/Output EXPAND!!D MCS-48 SystemII AA Read OO-Port #4 Write Port #5 10 or Port #6 Port #7Keyboard RD DisplayExpanded MCS-48 System Expansion Examples See Also ChapterMulti-Chip MCS-48 Systems Memory Bank Switching =====ll 8~~5Control Signal Summary Port CharacteristicsBUS Port Operations Port 2 Operations000 Page Page Instruction SET Instruction SET Subroutines Instruction SET Instruction SET Summary 8021 Instruction SET Summary RETDBF Symbols and Abbreviations UsedPSW ADD A,R r Add Register Contents to Accumulator ADD A,@R r Add Data Memory Contents to AccumulatorAddc A,R r Add Carry and Register Contents to Accumulator ADD A,#data Add Immediate Data to AccumulatorANL A,R r Logical and Accumulator With Register Mask Addc A,#data Add Carry and Immediate Data to AccumulatorANL A,@R r Logical and Accumulator With Memory Mask ANL A,#data Logical and Accumulator With Immediate Mask ANL A,#3+X/Y Andacc Contents with Value of EXP 3+X/YAnld Pp,A Logical and Port 4-7 With Accumulator Mask Andport 4 Contents With ACC BitsMOV RO,#50 Move 50DEC to Address INC RO Increment REG RET Return to Main Program10010101111 Contents of the accumulator are cleared to zero Cpla CPL Aacc Contents are COMPLE- Mented to11010 Flag 1 is cleared to zero F1-0 11 00 0 Flag 0 is cleared to zeroDA Aacc Adjusted to 00000001 with C SET AC 7 4 3 0 o 1 0 ADD SIX to Bits 010100001ADD SIX to Bits Overflow to CExample Decrement contents of external data memory location DEC Rr Decrement Register Not in 8021EN I Enable External Interrupt EN Tcnti Enable Timer/Counter Interrupt NotEnto ClK Enable Clock Output Not in 8021,8022 A,Pp Input Port or Data to AccumulatorINC Rr Increment Register INC a Increment AccumulatorINC @R r Increment Data Memory Location IputoPort 0 Data to Accumulator 8021, 8022 Only INS A,BUS Strobed Iput of BUS Data to AccumulatorJBb address Jump If Accumulator Bit is Set Not in 8021 JC address Jump If Carry Is SetJF1 address Jump If Flag 1 Is Set Not in 8021 JMP address Direct Jump Within 2K BlockJmpp @A Indirect Jump Within JNC address Jump If Carry Is Not SetJNI address Jump If Interrupt Input is Low Not in 8021 Jnto address Jump If Test 0 Is Low NotJNT1 address Jump If Test 1 Is Low JNZ address Jump If Accumulator Is Not ZeroJump to Timerroutine IFTF=1Jump to Location 53 DEC Jump to CountroutineMaV A,PSW Move PSW Contents to Accumulator Not in 8021 MaV A,R r Move Register Contents to AccumulatorMaV A,@R r Move Data Memory Contents to Accumulator Mev A, #data Move Immediate Data to AccumulatorMev A,T Move Timer/Counter Contents to Accumulator MaV @Rr,A Move Accumulator Contents to Data Memory Movo Pp,A Move Accumulator Data to Port Movo A,Pp Move Port 4-7 Data to AccumulatorMovp A,@A Move Current Page Data to Accumulator Maxdm Movx A,@R1 Move Contents of Location MOVP3 A,@A Move Page 3 Data to Accumulator Not in 8021,8022Not in 8021 Current page are Moved to ACCNOP The NOP Instruction ORL A,Rr Logical or Accumulator With Register MaskORL A,@Rr Logical or Accumulator With Memory Mask ORL A,#data Logical OFJ Accumulator With Immediate Mask8021 Outl Pp,A Output Accumulator Data to Port 1 or Retr Return With PSW Restore Not in 8021 Rrnc RR Anew ACC Contents are Example Assume carry is not set and accumulator containsRrtc RRC a Carry is SET and ACC ContainsSEL MBO Select Memory Bank JMP $+20Jump to Location 48 HEXStop Tcnt Stop Timer/Event-Counter 10110101011Jump to Routine Intif ACe BIT 3 is SET REG 7=8Strt CNT Start Event Counter Strt T Start TimerSwap a Swap Nibbles Within Accumulator XCH A,@R r Exchange Accumulator and Data Memory Contents XCH A,R r Exchange Accumulator-Register ContentsXchd A,@R r Exchange Accumulator and Data Memory 4-Bit Data XRL A,@R1 Xoracc Contents with Mask Location XRL A,Rr Logical XOR Accumulator With Register MaskXRL A,@Rr Logical XOR Accumulator With Memory Mask XRL A,#data Logical XOR Accumulator With Immediate MaskAppli~ation Examples Page Crystal Oscillator Mode LC Oscillator ModeIntroduction Driving from External SourceReset Application Examples~~J Rvv-i T1 Multiple Interrupt Sources Tf ~r Ii6Tt-2 A7 Serves as address latch17&A3 Xtali ROM=!-39TO Both 1/0 and RAM are addressed as data memoryReset This configuration is explained in sectionF1L Expander ~fd...L Pinnumbers are Different for~1~ DB6 rAdding 8 Input Lines Application Examples ·15Adding Output for KEYBOARD/DISPLAY Scanning JfL RT T T T TApplication Examples Emulator Circuit DESCRIPTION-6 MHZ Substitute aInterface to Drum Printer RAM TimerII Keyboard Display Microwave Oven Controller Double ADD Double SubtractDouble Load Double StoreApplication Examples Double Exchange Double Left Logical ShiftDouble Right Logical Shift Double Right Arithmetic ShiftApplication Examples Binary Multiply Interrupt HandlingApplication Examples Byte Processing System R1,ACPL Subtract Second from First INC 2sCOMPLEMENT and ADD8 MULTIPLY-ASSEMBLED by MCS-48 Macro Assembler See AP-49IIn ·1 APP\,JCATION Examples 16 x 8 DIVIDE-ASSEMBLED by MCS-48 Macro ASS.E.MBLERSEE AP-4916 x 8 DIVIDE-ASSEMBLED by MCS-48 Macro Assembler see AP-49 Page MCS-4STMComponent Page Hmos Single Component 8-BIT Microcomputer IIH!TUsed to enable data onto Address latch enable. ThisSignal occurs once during Program store enable. ThisS04SH/S04SH-1 /S035HL-1/S035H L-1 Inter 8048H/8048H-1/8035HL/8035HL.1 Absolute Maximum RATINGS·Port 2 Timing BUS Timing AS a Function of TCYS04SH/S04SH-1/S035HL/S035HL-1 WaveformsRead From External Data Memory 8035HL8048H/8048H·1/8035HL/8035HL·1 J3 Xtal ZPIN Configuration Logic Symbol Block Diagram RllPIN Configuration Logic Symbol Block Diagram8048/8035L/8748/8748-6/8748-8/8035/8035-8 PIN DescriptionAFN-Q1354A-03 All Except XTAL1, XTAL2, Reset Input High Voltage X1, X2, RESEiVOL =2.0 mA Output Low Voltage 10L = 1.8 mA===i---h·1 Characteristics Port 2 Timing Crystal Oscillator Mode LC Oscillator ModeDriving from External Source PROGRAMMING, VERIFYING, and Erasing the 8748 EpromTA = 2SOC ± SoC, Vee =SV ± S%, Voo = 2SV ± Verify .I.~---PROGRAM Waveforms for ProgrammingPROMPT-48 Microcomputer Design Aid, or Intel Corporation 108048/8748/8035L 108048/8748/8035L Operating Characteristics IDS0481S7481S035LAbsolute Maximum RATINGS· BUSP1, P2BUS, P1, P2TAW Address Setup to WR 260 TAD Address Setup to DataTOR Data Hold PSEN, RD to DataCharacteristics Top Port Control Setup Before Failing Edge of ProgTpL Port 2 I/O Data Setup TA= -40·Cto +85·C, Vcc=5V ±10%, Vss=OVCrystal Oscillator Mode Driving from External Source Reset+-----t XTALl ProgTA =25C ± 5C, Vee =5V ± 5%, Vee =25V ± TA = 25C ± 5C, Vee = 5V ± 5%, Vee = 25V ±Waveforms for Programming PROMPT-48 Microcomputer Design Aid. orInter Voo Lcoscillator ModeProgramming Verification IPH Unit Test ConditionsVoo Program Voltage High Level 24.0 2S.0 EA Program or Verify Voltage High Level 21.5 24.5 8748EA 5 M8048/M8748/M8035LM8048/M8748/M8035L Pin # ProgTcp Port Control Setup Before Falling TpL Port 2 1/0 Data SetupTpo Output Data Hold Time Tpp Prog Pulae Width TLP Port 2 1/0 Data Hold 120Characteristics ALE JI ~----r---I LAN D Operati NG Characteristics BUS, P1, P2Inter 80411803118031 8049/8039 Operating Characteristics Symbol Parameter Min Max UnitALE JIL --------..1.--1----L 18049/8039 Mask Programmable ROM External ROM or Eprom MHz OperationINr IntJ18049/8039 TilVIH1 BUS, RD, WR, PSEN, ALEVOL2 BUS, RD, WR, PSEN, ALE VOH1TAFC--1 I~OATING-I t=t or WaveformsOutput Data Setup Time 230 Port 2 1/0 Data Setup 300TA = -400C to +850 C, Vee = Voo = +5V ±10%, Vss = OV Unit Conditions NoteCrystal Oscillator Mode LC Oscillator Mode XT AL1PIN Configuration Logic Symbol Block Diagram 8021OC to 70C V1Hl Input High Voltage Xtal 1 & 2, T1VIH10% Input high voltage all except Xtal 1 T1, RESElALE XTAL28022 Reset Avss Prog POO-P07VTH Varef ANO,AN1 ALE Xtal8022 FzxIpAL---ooj·1 Port 2 TimingAID Converter Characteristics Analog Input TimingMnemonic for in-page Operation Analog Input 0, Analog Input TimerCNT Inter PIN Description GNDAbsolute Maximum Ratings ~~x 125 P20-P23 -- .....--X..... ...Jr 108243 14P5218243 GND18243 Tes # pins= 60 mA-+- 8 mA/pin = 7.5= 1 2 3 4 5 6 7 8 9 10 11 12Output Expander Timing 16,384·8IT ROM with Reset CE1CE2 ReadySymbol Parameter MIN MAX 8355/8355-2III ILO+- Al ~ Cl ~Output Mode Input Mode8355/8355·2 PIN Configuration Block Diagram Directly Compatible with SOS5A CPU8755AFUNCTIONAL PIN Definition 8755APROG/CE1 SA Programming Module Cross Reference Module Name USE with UPPUPPI41 UPP UP2121Symbol Parameter MIN MAX VIL 8755AComment Ready Hold TimeClock Specification for 8755A Prom Read, 1/0 Read and Write TimingWait State Timing Ready =0 ITA =OC to 70C Vee =5V ± 5% Vss =OV Specification ProgrammingVoo Programming Voltage during Write To Eprom Program Mode Timing Diagram Enable 8085A 8085A-28155-2 8156-28155/8156/8155-2/8156-2 Timer OUT8155/8156 PIN Functions Description 8156 Internal RegistersProgramming Command Register Reading the Status RegisterControl Input Mode Output Mode INPUT/OUTPUT SectionBFLowLow INTRLowHigh STB8155/8156/8155-2/8156-2 PcaTimer Section Example Program Interval Timer Interrupt Levels 8085A Minimum System ConfigurationWR AD ALE Symbol Parameter MIN MAX Units Test Conditions VIL Symbol Parameter MIN MAX UnitsRead Cycle Write Cycle8155/8156/8155-2/8156-2 WI\ J / jBasic Input Mode Basic Output ModePIN Configuration Block Diagram PIN NamesTruth Table for Power Down and Function Enable 8185/8185-2Operational Description Truth Table for Control and Data BUS PIN StatusAbsolute Maximum Ratings Comment8185/8185-2 Page Page SINGLE-COMPONENT 8-BIT Microcomputer 0INTRODUCTION 8051 FamilyMACRO-VIEW of the 8051 Architecture 8051 CPU Architecture1Interrupt System ON-CHIP Peripheral Functions21/0 Facilities 8031/8051/8751 3Timer/Event Counters 8031/8051/87518031/8051/8751 4Serial Communications~=- J~~====~ ~DATA 8031/8051/8751 Circuit ground potentialPsen XTAL1XTAL2 Family Development System and Software SupportSymbol Parameter Min Typ Max Units Universal Prom Programmer Personality Card UPP-851Workshop Insite Library12MHz Clock Data Memory Write Cycle Inter8031/8051/8751 8051 Instruction SET SummaryInter All mnemonics copyrlghted@ Intel CorporationPage Compatible MCS-48 Components PIN Configuration 1024 X 4 BIT Static RAM2114A Family Address -..II-------------i--l Symbol ParameterUnit Typical D.C. and .A.C. Characteristics Normauzed Access Time VS Supply Voltage2316E 16K 2K 8 ROM 2316E Data ----=HIGHZ~--~~~~~~~~~~-OU-T~TV-ALIO~~~JlJJI PIN Configuration PIN Connection During Read or ProgramBB Power Supply 5V±5% 5Vt.5% -5V±5% -5V±10% Operating CharacteristicsFamily Nco and A.C.OPERATING Conditions During ReadAddress to Output Delay 2708·1 limits 2708·6Limits UnitsInput Capacitance VIN = OVFamily WaveformsPIN Configuration Mode Selection PIN NamesProgramming CE = VIH. OE = VIL2716 Cout2716 Typical 16K Eprom System2716 Device OperationApproved 8086·2 MPU .. .Zero Wait StateTwo Line Control Industry Standard Pinout . .. Jedec8205 Ei==~ fEH2·E3 A13 --..,-H+-q E 8205Applications Eii-+-IH-+t-t rState Decoder Circuit Typical Characteristics \.. ~ ~TA = O·Cto + 75·C, Vee = 5V ± 5% MIN MAXSwitching Characteristics CharactristicsConditions of Test Test Load Test WaveformsPIN Configuration Logic Diagram IT osGD ~s ------- + H DB ---------- -- +iFunctional Description Il D+-+1 IE DBasic Schematic Symbols II. Gated Butter 3-StateGated Buffer DS2 , ------,----.J8212 Here the 8212 is used as the status latch for an 8080A VI. Output Port With Hand-ShakingAD2 Bossa AD4 AD5 AD6 AD7~DI, Stbdo LOW Order CLR8212 Output Currents 100mAInput Load Current, ACK, OS2, CR VF = A5V IOL = 15mAFfi IliSwitching Characteristics Typ. Max CIN 051 MD Input Capacitance 9pF 12pF052. CK. ACK. DI1-Dls Input Capacitance 5pF DOs Output Capacitance 8pFTCI II,D SGS821413214 Icex8214/3214 CapacitancesInte Test Conditions Test Load Circuit·BITPARALLEL Bidirectional BUS Driver 001Bidirectional Driver Control aatlng OlEN, CSWaveforms Characteristics OUT O---TIFI IF2 IRI IR2 VIL VIH Voli VOL2821618226 Applications of the 8216/82268282/8283 Octal Latch010 VCCPIN Definitions Operational Description PinD.scrlptlonVOL VOH TivovTshov TehozJJ\~ J/~~ 8282/8283 Intel VeeAo-A7 Bo- B7Characteristics for 8286/8287 Output Delay vs. Capacitance Jk~Output Page Page Synchronous and Asynchronous Operation Synchronous 5·8 Bit CharactersFeatures and Enhancements Capacitance pF CapacitanceIofl Bus Parameters !Note Input Waveforms for AC TestsMIN MAX Unit Programmable Interval Timer General VIIi -.,--.,qSystem Interface Control Word RegisterOperational Description GeneralProgramming Control Word Format825318253·5 Mode 2 Rate Generator =41 I---t--n --+LSB 8253/8253-5MSB Read Operation Chart Mode Register for Latching CountRead Operations Reading While CountingOe to 700 e Bus Parameters Note Input Waveforms for A.C. TestsRe.dCycle Write Timing825318253·5 Clock and Gate TimingPIN Configuration 8255A Block Diagram Programmable Peripheral Interface8255A18255A·5 8255A Functional Description8255A Basic Operation Face peripheral devices or structuresPIN Configuration PIN Names 8255A18255A·5Group a and Group B Controls Ports A, B, and CSingle Bit Set/Reset Feature Mode Selection8255A Operational Description Operating Modes Interrupt Control FunctionsMode 0 Port Definition Mode 0 Configurations8255AJ8255A·5 PA7·pAoII I I I, I0 I0 I0 Input Control Signal Definition TPHIBF Input Buffer Full F/F Intr Interrupt RequestOutput Control Signal Definition 10 I ·IOMXlXlIntea Inte BCombinations of Mode Bidirectional Bus 1/0 Control Signal DefinitionOutput Operations Input Operations8255.Al8255A·5 LtAOiErXtJ I 0\ \, I, erXtJ I0\30AFN-00744A-14 Mode Definition SummaryOnly Applications of the 8255A Printer InterfacePC, r MSBCapacitance Read MIN. MAX UnitCIR TwB TRIT LtR1BjSIB-Ii Programmable Interrupt Controller SP/ENInterrupts in Microcomputer Systems 8259A8259A Basic Functional Description Interrupt Request Register IRR and IN·SERVICE Register ISR Priority ResolverInterrupt Mask Register IMR INT Interrupt8259A 8259A Interface to Standard System BusCascade BUFFER/COMPARATOR Interrupt Sequence~O ~ ~ Disable Function Programming the 8259AGeneral Input Operation ReadInitialization Command Words 1 and 2 ICW1,ICW2 Initialization Command Word 3 ICW30 I 0 I 0 I 0 I 0 lID, liD, lIDo 8259AOperation Command Words OCWs Operation Control Word 1 OCW1Operation Control Word 2 OCW2 Operation Control Words Ocwi OcwaOJNTl Operation Command Word FormatR,-r-- I-i-Ioo r,-r,-r Special Mask Mode Buffered ModeFully Nested Mode Special Fully Nested ModeWord enabled onto the data bus during m5 is Automatic END of Interrupt Aeoi ModeRotating Priority Mode B Rotation by Software WolPriority Cell Simplified Logic Diagram Level Triggered ModeThis mode is programmed using bit 3 in ICW1 OH-++-+8272 Features 8272Registers CPU Interface Description8272 Polling Feature Reset to the Interrupt signalIntJ Command SET Command Descriptions Read DataWrite Data Transfer Capacity EN End of Cylinder Flag No No Data FlagWrite Deleted Data Read Deleted DataRead a Track ReadidScan Commands Recalibrate Sense Interrupt StatusSpecify Sense Drive StatusStatus Registers BIT Name Symbol Description UsaDC Characteristics VIL CLK & WR CLK VIHCINI» VIN=OVICY ~-----~---V Sel-I Timing Measurement ConditionsLI3 Block Oiagram8273, 8273·4, 8273·8 Brief Description of HDLC/SDLC Protocols32XCLi Flag DETProgrammable KEYBOARD/DISPLAY Interface RAMHardware Description 827918279-5Principles of Operation 827918279·5 Software Operation End Interrupt/Error Mode Set Status WordData Read Data WriteInterface Considerations Scanned Keyboard Mode, 2·Key Lockout===~ General Block Diagram ApplicationsVIL2 Symbol Test TYP MAXIIL1 Input Waveforms for A.C. Tests BUS Parameters8279 Scan Timing Scan Waveforms Display WaveformsGpib TALKER/LISTENER 8291 System Diagram 8291General Purpose Interface BUS Gpib General DescriptionAcds PacsAcrs PpasSH,AH,T,TE,L,LE,SR,RL,PP,C AH,CRemote Messages Received ATN SH,AH,T,TE,L,LE,PP,C DAB DACRemote Messages Sent ATN DAB DACDAV ENDAll Write Registers DontCareSPAS---SPAS Spasc Llcno LLO Lloc Interrupt RegistersMenting this feature, with 80 and Bi enabied from ITO ILO I 0 I 0 I 0 I 0 Admi Aomoi Provided for Command Pass Through RegisterSection on Parallel Poll Protocol Auxiliary Mode Register Auxiliary CommandsInternal Counter 2NFAuxiliary Register a Auxiliary Register BReset Procedure Parallel Poll Protocol8291 Using DMA 8291 to 8291A Software Compatibility Device Electrical Characteristics VOH-INTIlol IlohTwA~ Timing WaveformsGpib Timingsii Modified State Diagrams Figure A.1 State Diagrams next101 Response to ATN 200ns Interface Message Accept Time t Settling Time for Multiline Messages 21stTE,L,LE,C,CE Figure C-l -Wire Handshake Timing at Appendix CFigure C.2. Handshake Flowchart IIIL---,--11 ,--I 105Gpib Controller 106Ai1W Gpib Transceiver EOI BUS1BUS9 OATA1Mode 0 PIN Description =OVGpib NDAC* I/OTIL NrfoIeee Gpib Mode 2 PIN Description Mode 1 PIN DescriptionNdac Nrfd IeeeMode 3 PIN Description R1L LIENTiR1 Operating Characteristics 8293Absolute Maximum Ratings CapacitanceCharacteristics TA = O·Cto 70·C Vee= 5.0V ± 10% GND = OVTYP.· MAX ·118Output Loading Test Circuits 8293 Waveforms8294 8295 ·122====J 123UPI·41A Features Enhancements Mnemonic Description Bytes Cycles Signal DescriptionData Moves 8041 Al8641 Al8741 a VIU IU1Input and Output Waveforms for A.C. Tests Typical 8041/8741A CurrentRead OPERATION-DATA BUS Buffer Register Write OPERATION-DATA BUS Buffer RegisterCHARACTERISTICS-DMA CHARACTERISTICS-PORTWAVEFORMS-DMA PROGRAMMING, VERIFYING, and Erasing the 8741A Eprom VOOSpecification for Programming Timing Specification for ProgrammingVdol Program 8041Al8641 Al8741ASupport Products Page Microcomputer Development System CreditMODEL225 Functional Description 10-2InterMODEL225 System Components Integral CRTPeripheral Interface ControlSpecifications Notavailable on bus 110V, 60 Hz 5.9 Amp 220V, 50 Hz 3.0 Amp9800556 9800292Page Intellec Prompt MCS·48 Microcomputer Design AID Intellec Prompt Features Single Component Compu.terPrompt 48 Commands and Functions Intellec PromptIntellec Prompt Functional Description MCS-48 ProcessorsPrompt system Is running a user program User Interrupt causes an Interrupt only IfCycle Time tCY = 2.5,..s Clock 6 MHz ± 0.1% Ordering Information MCS·48 IN·CIRCUIT Emulator ~ L · ICE·49Memory Mapping GO from .START Till XDATA. Rslt WrittenICE·49 ISIS·IIEM1 Emulation Board EM1 EM1 Specifications DC Power Vcc5V ±5% Icc 300 mA maxOrdering Information MDS·EM1EM2 Emulation Board 40·PIN Socket Configuration EM2 Block Diagram EM2ANO AN1UPP-1P3 EM2MDS-EM2 Canadian Sales Offices SeptemberCanadian Distributors TAvnet Electronics McCormick Avenue Costa MesaIntJ Bowers Avenue International Sales and Marketing Offices International DISTRIBUTORS/REPRESENTATIVESInternational Sales and Marketing Offices INTEL$ Marketing OfficesCanadian Service Offices