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Intel mcs-48 manual MODEL225 Functional Description, 10-2

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MODEL225

FUNCTIONAL DESCRIPTION

Hardware Components

The Intellec Series 11/85 Model 225 is a highly- integrated microcomputer development system consisting of a CRT chassis with a 6-slot cardcage, power supply, fans, cables, single floppy disk drive, and two printed circuit cards. A separate, full ASCII keyboard is connected with a cable. A block diagram of the Model 225 is shown in Figure1.

CPU Cards - The master CPU card contains its own microprocessor, memory, I/O, interrupt and bus interface circuitry implemented with Intel's

high technology LSI components. Known as the integrated processor card (IPC), it occupies the first slot in the cardcage. A second slave CPU card is responsible for all remaining I/O control including the CRT and keyboard interface. This card, mounted on the rear panel, also contains its own microprocessor, RAM and ROM memory, and 1/0 interface logic, thus, in effect, creating a dual processor envi"ronment. Known as the 1/0 con- troller (IOC), the slave CPU card communicates with the ~PC over an 8-bit bidirectional data bus.

Expansion - Five remaining slots in the cardcage are available for system expansion. Additional expansion of 4 slots can be achieved through the addition of an Intellec Series II expansion chassis.

LOCAL

INTERRUPT

CONTROL

8259A

I t

•I

I

64K BYTES

4K BYTES

8·LEVEL

SERIAL

SERIAL

BAUD RATE

PRIORITY

PANEL

~

GENERATOR &

CHANNELO

CHANNEL1

RAM

ROM

INTERRUPT

CONTROL

8251A

8251A

REAL·TIMECLOCK

?

8259A

K?INTELLEC BUS

I

I

8253A

;J

I

I

BUS

PRIORITY

SYSTEM

8080A·2

8085A·2

BIDIRECTIONAL

CONTROLLER

RESOLUTION

CLOCKS

CPU

CPU

DRIVER

8219

1

I I

CABLE BUS

?

-.:.II

~

Y

8228

8253

DMA

8K RAM

SYSTEM

INTERVAL

CONTROLLER

TIMER

cp

9IOC BUS

t

f

t

8041A

CPU

....

,..

t

~

...

,..

,J

...

... ,..

?

PIO BUS

?

....

"..

....

"..

8

!

!

f

8271

8275

TAPE

TAPE

FLOPPY

CRT

KEYBOARD

PRINTER

PUNCH

READER

CONTROLLER

CONTROLLER

Figure 1. Intellec Series 11/85 Model 225 Microcomputer Development System Block Diagram

10-2

AFN-014248

Image 451

Intel mcs-48 manual MODEL225 Functional Description, 10-2

Contents

Page September MCS-48 Family of Single Chip Microcomputers UsersmanualPrompt BXPMultibus CreditTable of Contents 8051/8751/8031 Microcomputer ChaptersPacking Information Emulation BoardEmulation Board 10-19 UPP-103 Universal Prom Programmer Insite UsersLibraryPage Ntroduction Page Introduction to MCS-48 5.0 and 10.0 J,Lsec Cycle Versions Introduction8021 is code compatible but not pin compatible with Til IntroductionEprom Introduction Accumulator Function of a ComputerTypical Computer System Architecture of a CPUProgram Counter Jumps, Subroutines and the Stack Arithmetic/Logic Unit ALU Three levels of subroutines may be ac- commodatedInstruction Register and Decoder Address RegistersInstruction Fetch Control CircuitryComputer Operations TimingInput/Output Memory WriteInterrupts To the next instructions When finished the processor continues onMOV R2, #05 Step No. Hex Code Assembly Code MOV RO, #32Our machine language program then becomes Step Hex CodeCpla ADD A, REG ADD A, # ALFA*BETA/2SUB R7 Function Definition Hardware ConfigurationDeveloping An MCS-48 Based Product EducationPrompt Production Intellec Development SystemPage Single Component MCS-4S S~stem Page Architecture SummaryArithmetic Section ~BUS Location Single Component SystemInput/Output Single Component SystemSingle Component System Pointer R23+--1 R Jump ConditionsInterrupt Timing Oscillator As a TimerAs an Event Counter Clock and Timing CircuitsALE --f---+--+ Instruction 111LOVI BUS PCO·7 Power Down ModeRUN Stop Pin Description Number Function 00-07Designation ProgProgramming, Verifying and Erasing Eprom ResetSingle Component System Disabling Internal Program Memory ResetTest and Debug Single StepReading Internal Program Memory Following is a functional description of the major elements Program MemoryOscillator and Clock Timer/Event CounterQUASI-BIDIRECTIONAL Port Structure Input/Output CapabilitiesHigh Current Outputs 1 T1 InputExpanded I/O Jump Test Condition Instructions Accumulator ResetCarry Flag Timer Overflow Flag 10 CPUProgram Memory Functional SpecificationsData Memory See the 8021 description, .8, for a com- plete explanation 15Timer/Event CounterOscillator and Clock Port 0 Comparator InputsExpanded 1/0 High Current OutputsTest and Interrupt Inputs 1-3 VAC Analog to Digital Converter Ill19 CPU Expanded Page Expansion of Program Memory SummaryInterrupt Routines Expanded MCS-48 SystemROM AI? LatchLatch IOW Expansion of Data MemoryEXPAND!!D MCS-48 System Expansion of Input/OutputRead OO-Port #4 Write Port #5 10 or Port #6 Port #7 II AARD Display KeyboardExpansion Examples See Also Chapter Expanded MCS-48 SystemMulti-Chip MCS-48 Systems =====ll 8~~5 Memory Bank SwitchingPort 2 Operations Control Signal SummaryPort Characteristics BUS Port Operations000 Page Page Instruction SET Instruction SET Subroutines Instruction SET Instruction SET Summary 8021 RET Instruction SET SummaryDBF Symbols and Abbreviations UsedPSW ADD A,#data Add Immediate Data to Accumulator ADD A,R r Add Register Contents to AccumulatorADD A,@R r Add Data Memory Contents to Accumulator Addc A,R r Add Carry and Register Contents to AccumulatorANL A,R r Logical and Accumulator With Register Mask Addc A,#data Add Carry and Immediate Data to AccumulatorANL A,@R r Logical and Accumulator With Memory Mask ANL A,#data Logical and Accumulator With Immediate Mask ANL A,#3+X/Y Andacc Contents with Value of EXP 3+X/YAnld Pp,A Logical and Port 4-7 With Accumulator Mask INC RO Increment REG RET Return to Main Program Andport 4 ContentsWith ACC Bits MOV RO,#50 Move 50DEC to Address11 00 0 Flag 0 is cleared to zero 10010101111 Contents of the accumulator are cleared to zeroCpla CPL Aacc Contents are COMPLE- Mented to 11010 Flag 1 is cleared to zero F1-0Overflow to C DA Aacc Adjusted to 00000001 with C SETAC 7 4 3 0 o 1 0 ADD SIX to Bits 010100001 ADD SIX to BitsDEC Rr Decrement Register Not in 8021 Example Decrement contents of external data memory locationA,Pp Input Port or Data to Accumulator EN I Enable External InterruptEN Tcnti Enable Timer/Counter Interrupt Not Ento ClK Enable Clock Output Not in 8021,8022INC Rr Increment Register INC a Increment AccumulatorINC @R r Increment Data Memory Location JC address Jump If Carry Is Set IputoPort 0 Data to Accumulator 8021, 8022 OnlyINS A,BUS Strobed Iput of BUS Data to Accumulator JBb address Jump If Accumulator Bit is Set Not in 8021JNC address Jump If Carry Is Not Set JF1 address Jump If Flag 1 Is Set Not in 8021JMP address Direct Jump Within 2K Block Jmpp @A Indirect Jump WithinJNZ address Jump If Accumulator Is Not Zero JNI address Jump If Interrupt Input is Low Not in 8021Jnto address Jump If Test 0 Is Low Not JNT1 address Jump If Test 1 Is LowJump to Countroutine Jump to TimerroutineIFTF=1 Jump to Location 53 DECMev A, #data Move Immediate Data to Accumulator MaV A,PSW Move PSW Contents to Accumulator Not in 8021MaV A,R r Move Register Contents to Accumulator MaV A,@R r Move Data Memory Contents to AccumulatorMev A,T Move Timer/Counter Contents to Accumulator MaV @Rr,A Move Accumulator Contents to Data Memory Movo Pp,A Move Accumulator Data to Port Movo A,Pp Move Port 4-7 Data to AccumulatorMovp A,@A Move Current Page Data to Accumulator Current page are Moved to ACC Maxdm Movx A,@R1 Move Contents of LocationMOVP3 A,@A Move Page 3 Data to Accumulator Not in 8021,8022 Not in 8021ORL A,#data Logical OFJ Accumulator With Immediate Mask NOP The NOP InstructionORL A,Rr Logical or Accumulator With Register Mask ORL A,@Rr Logical or Accumulator With Memory Mask8021 Outl Pp,A Output Accumulator Data to Port 1 or Retr Return With PSW Restore Not in 8021 Contains Rrnc RR Anew ACC Contents areExample Assume carry is not set and accumulator contains Rrtc RRC a Carry is SET and ACC48 HEX SEL MBO Select Memory BankJMP $+20 Jump to LocationBIT 3 is SET REG 7=8 Stop Tcnt Stop Timer/Event-Counter10110101011 Jump to Routine Intif ACeStrt CNT Start Event Counter Strt T Start TimerSwap a Swap Nibbles Within Accumulator XCH A,@R r Exchange Accumulator and Data Memory Contents XCH A,R r Exchange Accumulator-Register ContentsXchd A,@R r Exchange Accumulator and Data Memory 4-Bit Data XRL A,#data Logical XOR Accumulator With Immediate Mask XRL A,@R1 Xoracc Contents with Mask LocationXRL A,Rr Logical XOR Accumulator With Register Mask XRL A,@Rr Logical XOR Accumulator With Memory MaskAppli~ation Examples Page Driving from External Source Crystal Oscillator ModeLC Oscillator Mode IntroductionApplication Examples Reset~~J Rvv-i T1 Multiple Interrupt Sources Ii6 Tf ~rTt-2 A7 Serves as address latch17&A3 ROM XtaliBoth 1/0 and RAM are addressed as data memory =!-39TOReset This configuration is explained in sectionF1L Expander Pinnumbers are Different for ~fd...LDB6 r ~1~Adding 8 Input Lines ·15 Application ExamplesAdding Output for KEYBOARD/DISPLAY Scanning RT T T T T JfLSubstitute a Application Examples Emulator Circuit DESCRIPTION-6 MHZInterface to Drum Printer RAM TimerII Keyboard Display Microwave Oven Controller Double Store Double ADDDouble Subtract Double LoadDouble Right Arithmetic Shift Application Examples Double ExchangeDouble Left Logical Shift Double Right Logical ShiftInterrupt Handling Application Examples Binary Multiply2sCOMPLEMENT and ADD Application Examples Byte Processing SystemR1,A CPL Subtract Second from First INCSee AP-49 8 MULTIPLY-ASSEMBLED by MCS-48 Macro AssemblerIIn ·1 16 x 8 DIVIDE-ASSEMBLED by MCS-48 Macro ASS.E.MBLERSEE AP-49 APP\,JCATION Examples16 x 8 DIVIDE-ASSEMBLED by MCS-48 Macro Assembler see AP-49 Page MCS-4STMComponent Page IIH!T Hmos Single Component 8-BIT MicrocomputerProgram store enable. This Used to enable data ontoAddress latch enable. This Signal occurs once duringS04SH/S04SH-1 /S035HL-1/S035H L-1 Absolute Maximum RATINGS· Inter 8048H/8048H-1/8035HL/8035HL.1BUS Timing AS a Function of TCY Port 2 Timing8035HL S04SH/S04SH-1/S035HL/S035HL-1Waveforms Read From External Data MemoryJ3 Xtal Z 8048H/8048H·1/8035HL/8035HL·1Rll PIN Configuration Logic Symbol Block DiagramBlock Diagram PIN Configuration Logic SymbolPIN Description 8048/8035L/8748/8748-6/8748-8/8035/8035-8AFN-Q1354A-03 Output Low Voltage 10L = 1.8 mA All Except XTAL1, XTAL2, ResetInput High Voltage X1, X2, RESEi VOL =2.0 mA===i---h·1 Characteristics Port 2 Timing PROGRAMMING, VERIFYING, and Erasing the 8748 Eprom Crystal Oscillator ModeLC Oscillator Mode Driving from External SourceTA = 2SOC ± SoC, Vee =SV ± S%, Voo = 2SV ± Verify .I.~---PROGRAM Waveforms for ProgrammingPROMPT-48 Microcomputer Design Aid, or Intel Corporation 108048/8748/8035L 108048/8748/8035L BUSP1, P2BUS, P1, P2 Operating CharacteristicsIDS0481S7481S035L Absolute Maximum RATINGS·PSEN, RD to Data TAW Address Setup to WR260 TAD Address Setup to Data TOR Data HoldTA= -40·Cto +85·C, Vcc=5V ±10%, Vss=OV CharacteristicsTop Port Control Setup Before Failing Edge of Prog TpL Port 2 I/O Data SetupProg Crystal Oscillator Mode Driving from External SourceReset +-----t XTALlTA = 25C ± 5C, Vee = 5V ± 5%, Vee = 25V ± TA =25C ± 5C, Vee =5V ± 5%, Vee =25V ±PROMPT-48 Microcomputer Design Aid. or Waveforms for ProgrammingInter Voo Lcoscillator ModeProgramming Verification EA Program or Verify Voltage High Level 21.5 24.5 8748 IPHUnit Test Conditions Voo Program Voltage High Level 24.0 2S.0M8048/M8748/M8035L EA 5M8048/M8748/M8035L Prog Pin #TLP Port 2 1/0 Data Hold 120 Tcp Port Control Setup Before FallingTpL Port 2 1/0 Data Setup Tpo Output Data Hold Time Tpp Prog Pulae WidthALE JI ~----r---I L CharacteristicsBUS, P1, P2 AN D Operati NG CharacteristicsInter 80411803118031 8049/8039 Symbol Parameter Min Max Unit Operating CharacteristicsALE JIL --------..1.--1----L Mask Programmable ROM External ROM or Eprom MHz Operation 18049/8039INr Til IntJ18049/8039BUS, RD, WR, PSEN, ALE VOH1 VIH1BUS, RD, WR, PSEN, ALE VOL2Waveforms TAFC--1 I~OATING-I t=t orUnit Conditions Note Output Data Setup Time 230Port 2 1/0 Data Setup 300 TA = -400C to +850 C, Vee = Voo = +5V ±10%, Vss = OVXT AL1 Crystal Oscillator Mode LC Oscillator Mode8021 PIN Configuration Logic Symbol Block DiagramT1, RESEl OC to 70CV1Hl Input High Voltage Xtal 1 & 2, T1 VIH10% Input high voltage all except Xtal 1XTAL2 ALE8022 Varef ANO,AN1 ALE Xtal Reset AvssProg POO-P07 VTHFzx 8022Port 2 Timing IpAL---ooj·1Analog Input Timing AID Converter CharacteristicsMnemonic for in-page Operation Analog Input 0, Analog Input TimerCNT Inter GND PIN DescriptionAbsolute Maximum Ratings ~~x 125 P20-P23 -- .....--X..... ...Jr 14P52 108243GND 1824318243 Tes 1 2 3 4 5 6 7 8 9 10 11 12 # pins= 60 mA-+- 8 mA/pin = 7.5=Output Expander Timing 16,384·8IT ROM with Ready ResetCE1 CE2ILO Symbol Parameter MIN MAX8355/8355-2 IIICl ~ +- Al ~Output Mode Input Mode8355/8355·2 Directly Compatible with SOS5A CPU PIN Configuration Block Diagram8755AFUNCTIONAL PIN Definition 8755APROG/CE1 UPP UP2121 SA Programming Module Cross Reference Module Name USE withUPP UPPI41Ready Hold Time Symbol Parameter MIN MAX VIL8755A CommentProm Read, 1/0 Read and Write Timing Clock Specification for 8755AWait State Timing Ready =0 ITA =OC to 70C Vee =5V ± 5% Vss =OV Specification ProgrammingVoo Programming Voltage during Write To Eprom Program Mode Timing Diagram 8156-2 Enable8085A 8085A-2 8155-28155/8156/8155-2/8156-2 Timer OUT8155/8156 PIN Functions 8156 Internal Registers DescriptionReading the Status Register Programming Command RegisterSTB Control Input Mode Output ModeINPUT/OUTPUT Section BFLowLow INTRLowHighPca 8155/8156/8155-2/8156-2Timer Section Example Program Interval Timer Interrupt Levels 8085A Minimum System ConfigurationWR AD ALE Symbol Parameter MIN MAX Units Test Conditions VIL MIN MAX Units Symbol ParameterWrite Cycle Read CycleWI\ J / j 8155/8156/8155-2/8156-2Basic Output Mode Basic Input ModePIN Names PIN Configuration Block DiagramTruth Table for Control and Data BUS PIN Status Truth Table for Power Down and Function Enable8185/8185-2 Operational DescriptionComment Absolute Maximum Ratings8185/8185-2 Page Page SINGLE-COMPONENT 8-BIT Microcomputer 8051 CPU Architecture 0INTRODUCTION8051 Family MACRO-VIEW of the 8051 Architecture1Interrupt System ON-CHIP Peripheral Functions21/0 Facilities 8031/8051/8751 8031/8051/8751 3Timer/Event Counters4Serial Communications 8031/8051/8751~=- J~~====~ ~DATA Circuit ground potential 8031/8051/8751Family Development System and Software Support PsenXTAL1 XTAL2Insite Library Symbol Parameter Min Typ Max UnitsUniversal Prom Programmer Personality Card UPP-851 Workshop12MHz Clock Data Memory Write Cycle 8051 Instruction SET Summary Inter8031/8051/8751All mnemonics copyrlghted@ Intel Corporation InterPage Compatible MCS-48 Components 1024 X 4 BIT Static RAM PIN Configuration2114A Family Address -..II-------------i--l Symbol ParameterUnit Normauzed Access Time VS Supply Voltage Typical D.C. and .A.C. Characteristics2316E 16K 2K 8 ROM 2316E Data ----=HIGHZ~--~~~~~~~~~~-OU-T~TV-ALIO~~~JlJJI PIN Connection During Read or Program PIN ConfigurationNco and A.C.OPERATING Conditions During Read BB Power Supply 5V±5% 5Vt.5% -5V±5% -5V±10%Operating Characteristics FamilyVIN = OV Address to Output Delay2708·1 limits 2708·6Limits Units Input CapacitanceWaveforms FamilyPIN Names PIN Configuration Mode SelectionCE = VIH. OE = VIL ProgrammingCout 2716Typical 16K Eprom System 2716Device Operation 2716Industry Standard Pinout . .. Jedec Approved8086·2 MPU .. .Zero Wait State Two Line Control8205 Ei==~ fEH2·E3 Eii-+-IH-+t-t r A13 --..,-H+-q E8205 ApplicationsState Decoder Circuit MIN MAX Typical Characteristics\.. ~ ~ TA = O·Cto + 75·C, Vee = 5V ± 5%Test Waveforms Switching CharacteristicsCharactristics Conditions of Test Test LoadDB ---------- -- +i PIN Configuration Logic DiagramIT os GD ~s ------- + HIE D Functional DescriptionIl D +-+1DS2 , ------,----.J Basic Schematic SymbolsII. Gated Butter 3-State Gated Buffer8212 VI. Output Port With Hand-Shaking Here the 8212 is used as the status latch for an 8080ACLR AD2Bossa AD4 AD5 AD6 AD7 ~DI, Stbdo LOW OrderIOL = 15mA 8212Output Currents 100mA Input Load Current, ACK, OS2, CR VF = A5VIli FfiDOs Output Capacitance 8pF Switching CharacteristicsTyp. Max CIN 051 MD Input Capacitance 9pF 12pF 052. CK. ACK. DI1-Dls Input Capacitance 5pFTCI SGS II,DIcex 821413214Capacitances 8214/3214Test Conditions Test Load Circuit Inte001 ·BITPARALLEL Bidirectional BUS DriverControl aatlng OlEN, CS Bidirectional DriverOUT O---T Waveforms CharacteristicsVoli VOL2 IFI IF2 IRI IR2 VIL VIHApplications of the 8216/8226 821618226VCC 8282/8283Octal Latch 010PinD.scrlptlon PIN Definitions Operational DescriptionTehoz VOL VOHTivov TshovJJ\~ J/~~ 8282/8283 Vee IntelBo- B7 Ao-A7Characteristics for 8286/8287 Jk~ Output Delay vs. CapacitanceOutput Page Page Synchronous 5·8 Bit Characters Synchronous and Asynchronous OperationFeatures and Enhancements Capacitance pF CapacitanceIofl Input Waveforms for AC Tests Bus Parameters !NoteMIN MAX Unit Programmable Interval Timer VIIi -.,--.,q GeneralControl Word Register System InterfaceControl Word Format Operational DescriptionGeneral Programming825318253·5 =41 I---t--n --+ Mode 2 Rate GeneratorLSB 8253/8253-5MSB Reading While Counting Read Operation ChartMode Register for Latching Count Read OperationsOe to 700 e Write Timing Bus Parameters NoteInput Waveforms for A.C. Tests Re.dCycleClock and Gate Timing 825318253·5Programmable Peripheral Interface PIN Configuration 8255A Block DiagramFace peripheral devices or structures 8255A18255A·58255A Functional Description 8255A Basic OperationPorts A, B, and C PIN Configuration PIN Names8255A18255A·5 Group a and Group B ControlsSingle Bit Set/Reset Feature Mode Selection8255A Operational Description Interrupt Control Functions Operating ModesMode 0 Configurations Mode 0 Port DefinitionPA7·pAo 8255AJ8255A·5II I I I, I0 I0 I0 Intr Interrupt Request Input Control Signal DefinitionTPH IBF Input Buffer Full F/FInte B Output Control Signal Definition10 I ·IOMXlXl InteaInput Operations Combinations of ModeBidirectional Bus 1/0 Control Signal Definition Output OperationsLtAOi 8255.Al8255A·5\, I, erXtJ I0\ ErXtJ I 0\30AFN-00744A-14 Mode Definition SummaryOnly Printer Interface Applications of the 8255AMSB PC, rCapacitance MIN. MAX Unit ReadCIR TRIT LtR1Bj TwBSIB-Ii SP/EN Programmable Interrupt ControllerInterrupts in Microcomputer Systems 8259A8259A Basic Functional Description INT Interrupt Interrupt Request Register IRR and IN·SERVICE Register ISRPriority Resolver Interrupt Mask Register IMRInterrupt Sequence 8259A8259A Interface to Standard System Bus Cascade BUFFER/COMPARATOR~O ~ ~ Input Operation Read Disable FunctionProgramming the 8259A GeneralInitialization Command Word 3 ICW3 Initialization Command Words 1 and 2 ICW1,ICW28259A 0 I 0 I 0 I 0 I 0 lID, liD, lIDoOcwa Operation Command Words OCWsOperation Control Word 1 OCW1 Operation Control Word 2 OCW2 Operation Control Words OcwiOJNTl Operation Command Word FormatR,-r-- I-i-Ioo r,-r,-r Special Fully Nested Mode Special Mask ModeBuffered Mode Fully Nested ModeWol Word enabled onto the data bus during m5 isAutomatic END of Interrupt Aeoi Mode Rotating Priority Mode B Rotation by SoftwareOH-++-+ Priority Cell Simplified Logic DiagramLevel Triggered Mode This mode is programmed using bit 3 in ICW18272 Description Features8272 Registers CPU Interface8272 Reset to the Interrupt signal Polling FeatureIntJ Command SET Read Data Command DescriptionsTransfer Capacity EN End of Cylinder Flag No No Data Flag Write DataReadid Write Deleted DataRead Deleted Data Read a TrackScan Commands Sense Drive Status RecalibrateSense Interrupt Status SpecifyUsa Status Registers BIT Name Symbol DescriptionVIN=OV DC CharacteristicsVIL CLK & WR CLK VIH CINI»ICY ~-----~---V Timing Measurement Conditions Sel-IBlock Oiagram LI3Brief Description of HDLC/SDLC Protocols 8273, 8273·4, 8273·8Flag DET 32XCLiRAM Programmable KEYBOARD/DISPLAY InterfaceHardware Description 827918279-5Principles of Operation 827918279·5 Software Operation Data Write End Interrupt/Error Mode SetStatus Word Data ReadScanned Keyboard Mode, 2·Key Lockout Interface Considerations===~ Applications General Block DiagramVIL2 Symbol Test TYP MAXIIL1 BUS Parameters Input Waveforms for A.C. Tests8279 Display Waveforms Scan Timing Scan WaveformsGpib TALKER/LISTENER 8291 General Description System Diagram8291 General Purpose Interface BUS GpibPpas AcdsPacs AcrsDAC SH,AH,T,TE,L,LE,SR,RL,PP,CAH,C Remote Messages Received ATN SH,AH,T,TE,L,LE,PP,C DABEND Remote Messages Sent ATN DABDAC DAVDontCare All Write RegistersInterrupt Registers SPAS---SPAS Spasc Llcno LLO LlocMenting this feature, with 80 and Bi enabied from ITO ILO I 0 I 0 I 0 I 0 Admi Aomoi Provided for Command Pass Through RegisterSection on Parallel Poll Protocol Auxiliary Commands Auxiliary Mode RegisterAuxiliary Register B Internal Counter2NF Auxiliary Register aParallel Poll Protocol Reset Procedure8291 Using DMA 8291 to 8291A Software Compatibility Iloh Device Electrical CharacteristicsVOH-INT IlolTiming Waveforms TwA~Gpib Timingsii Figure A.1 State Diagrams next Modified State Diagrams101 Response to ATN 200ns Interface Message Accept Time t Settling Time for Multiline Messages 21stTE,L,LE,C,CE Appendix C Figure C-l -Wire Handshake Timing atFigure C.2. Handshake Flowchart 105 IIIL---,--11 ,--I106 Gpib ControllerAi1W Gpib Transceiver OATA1 EOIBUS1 BUS9NDAC* I/O Mode 0 PIN Description=OV GpibTIL NrfoIeee Gpib Mode 2 PIN Description Mode 1 PIN DescriptionNdac Ieee NrfdMode 3 PIN Description LIEN R1LTiR1 Capacitance Operating Characteristics8293 Absolute Maximum Ratings·118 CharacteristicsTA = O·Cto 70·C Vee= 5.0V ± 10% GND = OV TYP.· MAXOutput Loading Test Circuits Waveforms 82938294 ·122 8295123 ====JUPI·41A Features Enhancements Mnemonic Description Bytes Cycles Signal DescriptionData Moves 8041 Al8641 Al8741 a IU1 VIUWrite OPERATION-DATA BUS Buffer Register Input and Output Waveforms for A.C. TestsTypical 8041/8741A Current Read OPERATION-DATA BUS Buffer RegisterCHARACTERISTICS-DMA CHARACTERISTICS-PORTWAVEFORMS-DMA VOO PROGRAMMING, VERIFYING, and Erasing the 8741A EpromSpecification for Programming Timing Specification for ProgrammingVdol 8041Al8641 Al8741A ProgramSupport Products Page Credit Microcomputer Development System10-2 MODEL225 Functional DescriptionControl InterMODEL225 System ComponentsIntegral CRT Peripheral InterfaceSpecifications 9800292 Notavailable on bus110V, 60 Hz 5.9 Amp 220V, 50 Hz 3.0 Amp 9800556Page Intellec Prompt MCS·48 Microcomputer Design AID Single Component Compu.ter Intellec Prompt FeaturesIntellec Prompt Prompt 48 Commands and FunctionsMCS-48 Processors Intellec Prompt Functional DescriptionPrompt system Is running a user program User Interrupt causes an Interrupt only IfCycle Time tCY = 2.5,..s Clock 6 MHz ± 0.1% Ordering Information MCS·48 IN·CIRCUIT Emulator ICE·49 ~ L ·GO from .START Till XDATA. Rslt Written Memory MappingISIS·II ICE·49EM1 Emulation Board EM1 MDS·EM1 EM1 SpecificationsDC Power Vcc5V ±5% Icc 300 mA max Ordering InformationEM2 Emulation Board AN1 40·PIN Socket Configuration EM2 Block DiagramEM2 ANOUPP-1P3 EM2MDS-EM2 September Canadian Sales OfficesTAvnet Electronics McCormick Avenue Costa Mesa Canadian DistributorsIntJ International DISTRIBUTORS/REPRESENTATIVES Bowers Avenue International Sales and Marketing OfficesINTEL$ Marketing Offices International Sales and Marketing OfficesCanadian Service Offices