Intel mcs-48 manual INr, PIN Description

inter18049/8039

PIN DESCRIPTION

Designation

Vss

Vee

Vee

MaG

P1Q.P17

Port 1

P2O-P27

Port 2

00-07

BUS

TO

Pin # Function

20Circuit GND pOtential

26+5V during operation. low power standby pin.

40Main power supply; +5V during operation.

25Output strobe for 8243 1/0 expander.

27·34 B-bit quasi-bidirectional port.

21-24 B-bit quasi-bidirectional port_

35-38P20-P23 contain the four high order program counter bits during an external program memory fetch and serve as a 4-bit 1/0 expander bus for 8243

12-19 True bidirectional port which can be written or read synchronously using the RD, WR strobes. The port can also be statically latched.

Contains the 8 low order program counter bits during an external program memory fetch, and receives the addressed instruction under the controlof PSEN. Also contains the address and data during an external RAM data store instruction, under control of ALE, RD, and WR.

Input pin testable using the con- ditional transfer instructions JTO and JNTO. TO can be designated as a clock output using ENTO ClK instruction.

Designation	Pin #	Function
RD	8	Output strobe activated during a
		BUS read. Can be used to enable
		data onto the BUS from an external
		device.
		Used as a Read Strobe to External
		Data Memory. (Active low)
RESET	4	Input which is used to initialize the
		processor. Also used during verifi-
		cation, and power down. (Active
		low) (Non TTL VIH)
WR	10	Output strobe during a BUS write.
		(Active low)
		Used as write strobe to External
		Data Memory.
ALE	11	Address latch Enable. This signal
		occurs once dur ing each cycle and
		is useful as a clock output.
		The negative edge of ALE strobes
		address into external data and pro-
		gram memory.
PSEN	9	Program Store Enable. This output
		occurs only during a fetch to exter-
		nal program memory. (Active low)

SS5 Single step input can be used in con- junction with ALE to "single step" the processor through each in- struction. (Active low)

EA	7	External Access input which forces
		all program memory fetches to re-
		ference external memory. Useful
		for emulation and debug, and
		essential for testing and program

Tl	39	Input pin testable using the JT1,
		and JNT1 instructions. Can be des-
		ignated the timer lcounter input using
iNr		the STRT CNT instruction.
	6	Interrupt input. Initiates an inter-
		rupt if interrupt is enabled. Inter-

rupt is disabled after a reset. Also testable with conditional jump instruction. (Active low)

		verification. (Active high)
XTAL1	2	One side of crystal input for inter-
		nal oscillator. Also input for exter-
		nal source. (Not TTL Compatible)
XTAl2	3	Other side of crystal input.

6-42 AFN-00737-02