Intel mcs-48 manual S04SH/S04SH-1 /S035HL-1/S035H L-1

S04SH/S04SH-1 /S035HL-1/S035H L-1

INSTRUCTION SET

Accumulator
Mnemonic	Description	Bytes	Cycles
ADD A, R	Add register to A	I	I
ADD A,@R	Add data memory to A	I	I
ADD A, # data	Add immediate to A	2	2
ADDCA, R	Add register with carry	I	I
ADDCA,@R	Add data memory with carry	I	I
ADDC A, # data	Add immediate with carry	2	2
ANL A, R	And register to A	I	I
ANL A,@R	And data memory to A	I	I
ANL A, # data	And immediate to A	2	2
ORL A, R	Or register to A	I	I
ORL A@R	Or data memory to A	I	I
ORL A, # data	Or immediate to A	2	2
XRL A, R	Exclusive or register to A	I	I
XRLA,@R	Exclusive or data memory to A	I	I
XRL, A, # data Exclusive or immediate to A		2	2
INC A	Increment A	I	I
DEC A	Decrement A	I	I
CLR A	Clear A	I	I
CPL A	Complement A	I	I
DA A	Decimal adjust A	I	I
SWAP A	Swap nibbles of A	I	I
RL A	Rotate A left	I	I
RLC A	Rotate A left through carry	I	I
RR A	Rotate A right	I	I
RRCA	Rotate A right through carry	I	I
Input/Output
Mnemonic	Description	Bytes	Cycles
IN A, P	Input port to A	I	2
OUTL P, A	Output A to port	I	2
ANL p, # data	And immediate to port	2	2
ORL P, # data	Or immediate to port	2	2
INS A, BUS	Input BUS to A	I	2
OUTL BUS, A	Output A to BUS	I	2
ANL BUS, # data And immediate to BUS		2	2
ORL BUS, # data Or immediate to BUS		2	2
MOVD A,P	Input expander port to A	I	2
MOVD p, A	Output A to expander port	I	2
ANLD P, A	And A to expander port	I	2
ORLO p, A	Or A to expander port	I	2
Registers
Mnemonic	Description	Bytes	Cycles
INC R	Increment register	I	I
INC@R	Increment data memory	I	1
DEC R	Decrement register	I	I
Branch
Mnemonic	Description	Bytes	Cycles
JMP addr	Jump unconditional	2	2
JMPP@A	Jump indirect	I	2
DJNZ R, addr	Decrement register and skip	2	2
JC addr	Jump on carry = 1	2	2
JNC addr	Jump on carry =0	2	2
JZ addr	Jump on A zero	2	2
JNZ addr	Jump on A not zero	2	2
JTO addr	Jump on TO = I	2	2
JNTO addr	Jump on TO = a	2	2
JTI addr	Jump on T1 = 1	2	2
JNTI addr	Jump on TI = a	2	2
JFO addr	Jump on FO =1	2	2
JFI addr	Jump on FI = I	2	2
JTF addr	Jump on timer flag	2	2
JNI addr	Jump on INT = 0	2	2
JBb addr	Jump on accumulator bit	2	2

Subroutine
Mnemonic	Description	Bytes Cycles
CALL addr	Jump to subroutine	2	2
RETR	Return		2
RETR	Return and restore status
Flags
Mnemonic	Description	Bytes Cycles
CLR C	Clear carry	I	I
CPL C	Complement carry	I	I
CLR FO	CLear flag 0	I	I
CPL Fa	Complement flag 0	I	I
CLR FI	Clear flag I	I	I
CPL FI	Complement flag 1	I	I
Data Moves
Mnemonic	Description	Bytes Cycles
MOVA, R	Move register to A	I	1
MOVA,@R	Move data memory to A	I	I
MOV A, # data	Move immediate to A	2	2
MOV R. A	Move A to register	I	I
MOV@R.A	Move A to data memory	I	I
MOV R. # data	Move immediate to register	2	2
MOV @R, #data	Move immediate to data memory	2	2
MOVA, PSW	Move PSW to A	I	I
MOV PSW, A	Move A to PSW	I	I
XCH A, R	Exchange A and register	I	I
XCH A,@R	Exchange A and data memory	I	I
XCHDA,@R	Exchange nibble of A and	I
	register
MOVX A,@R	Move external data memory to A	I	2
MOVX@R,A	Move A to external data memory	I	2
MOVPA,@A	Move to A from current page	I	2
MOVP3A, @	Move to A from page 3	I	2
Timer/Counter
Mnemonic	Description	Bytes Cycles
MOVA, T	Read timer/counter	I	I
MOVT, A	Load timer/counter	I	I
STRT T	Start timer	I	I
STRT CNT	Start counter	I	I
STOP TCNT	Stop timer/counter	I	I
EN TCNTI	Enable timer/counter interrupt	I	I
DIS TCNTI	Disable timer/counter interrupt	I	1
Control
Mnemonic	Description	Byles, Cycles
EN I	Enable external interrupt	I	I
DIS I	Disable external interrupt	I	I
SEL RBO	Select register bank a	I	I
SEL RBI	Select register bank 1	I	I
SEL MBO	Select memory bank a	I	I
SEL MBI	Select memory bank 1	I	I
ENT aCLK	Enable clock output on TO	I	I
Mnemonic	Description	Byles Cycles
NOP	No operation	I	I

6-3 AFN-01491A-03