8291

GPIB Addressing

Each device connected to the GPIB must have at least one address whereby the controller device in charge of the bus can configure it to talk, listen, or send status. An 8291 implementation of the GPIB offers the user three addressing modes from which the device can be initialized for each application. The first of these modes allows for the device to have two separate primary addresses. The

second mode allows the user to implement a single talker/listener with a two byte address (primary address + secondary address). The third mode again allows for two distinct addresses but in this instance, they can each have a two-byte address. However, this mode requires that the secondary addresses be passed to the microprocessor for verification. These three addressing schemes are des- cribed in more detail in the discussion of the Address registers.

TABLE 1.

 

 

IEEE 488 INTERFACE STATE MNEMONICS

 

Mnemonic

State Represented

 

Mnemonic

State Represented

 

ACDS

Accept Data State

 

PACS

Parallel Poll Addressed to Configure State

 

ACRS

Acceptor Ready State

 

PPAS

Parallel Poll Active State

 

AIDS

Acceptor Idle State

 

PPIS

Parallel Poll Idle State

 

ANRS

Acceptor Not Ready State

 

PPSS

Parallel Poll Standby State

 

APRS

Affirmative Poll Response State

 

PUCS

Parallel Poll Unaddressed to Configure State

 

AWNS

Acceptor Wait for New Cycle State

 

 

 

------------------------ ,

REMS

Remote State

I

CACS

Controller Active State

I

RWLS

Remote With Lockout State

: CADS

Controller Addressed State

I

SACS

System Control Active State

I

CAWS

Controller Active Wait State

I

SDYS

Source Delay State

I

CIDS

Controller Idle State

I

SGNS

Source Generate State

I

CPPS

Controller Parallel Poll State

I

SIAS

System Control Interface Clear Active State

I

CPWS

Controller Parallel Poll Wait State

I

SIDS

Source Idle State

: CSBS

Controller Standby State

:

SIIS

System Control Interface Clear Idle State

I

CSNS

Controller Service Not Requested State

I

SINS

System Control Interface Clear Not Active State

I

CSRS

Controller Service Requested State

I

SIWS

Source Idle Wait State

I

CSWS

Controller Synchronous Wait State

I

SNAS

System Control Not Active State

L~T~~ _

~~t.':?~~TI:a~s!:.r~t~t~ ______ J

SPAS

Serial Poll Active State

 

DCAS

Device Clear Active State

 

SPIS

Serial Poll Idle State

 

DCIS

Device Clear Idle State

 

SPMS

Serial Poll Mode State

 

DTAS

Device Trigger Active State

 

SRAS

System Control Remote Enable Active State

 

OTIS

Device Trigger Idle State

 

SRIS

System Control Remote Enable Idle State

 

LACS

Listener Active State

 

SRNS

System Control Remote Enable Not Active State

 

 

SRQS

Service Request State

 

LADS

Listener Addressed State

 

 

 

STRS

Source Transfer State

 

LIDS

Listener Idle State

 

 

 

SWNS

Source Wait for New Cycle State

 

LOCS

Local State

 

 

 

 

 

 

LPAS

Listener Primary Addressed State

 

TACS

Talker Active State

 

LPIS

Listener Primary Idle State

 

TAOS

Talker Addressed State

 

LWLS

Local With Lockout State

 

TIDS

Talker Idle State

 

NPRS

Negative Poll Response State

 

TPIS

Talker Primary Idle State

 

 

 

 

------ The Controller function is implemented on the Intel® 8292.

9-85

Page 400
Image 400
Intel mcs-48 Acds, Pacs, Acrs, Ppas, Aids, Ppis, Anrs, Ppss, Aprs, Pucs, Awns, Rems, Cacs, Rwls, Cads, Sacs, Caws, Sdys