inter

8212

8-BIT INPUT/OUTPUT PORT

Fully Parallel8-Bit Data Register and Buffer

Service Request Flip-Flop for

Interrupt Generation

Low Input Load Current - .2SmA Max.

Three State Outputs

Outputs Sink 1SmA

3.6SV Output High Voltage for Direct Interface to 8008, 8080A, or 808SA CPU

Asynchronous Register Clear

Replaces Buffers, Latches and Multiplexers in Microcomputer Systems

Reduces System Package Count

The 8212 input/output port consists of an 8-bit latch with 3-state output buffers along with control and device selection logic. Also included is a service request flip-flop for the generation and control of interrupts to the microprocessor.

The device is multi mode in nature. It can be used to implement latches, gated buffers or multiplexers. Thus, all of the principal peripheral and input/output functions of a microcomputer system can be implemented with this device.

PIN CONFIGURATION

LOGIC DIAGRAM

 

 

 

SERVICE A~UEST FF

 

os,

vee

 

 

MO

INT

 

 

01,

01.

IT> os,

 

DO,

DO.

 

[i]> oS2

 

01 2

01 7

 

 

 

00 2

007

[[> Mo -----t-<H_~

 

01 3

DI.

ID> STB ----+--;_J

 

003

DO.

OUTPUT

 

01.

01 5

 

BUFFER

 

 

DO.

005

IT> 0', --------- ++t

 

STe

CLR

 

 

 

GNO

OS2

OATA LATCH

 

 

 

 

 

[B>o', ------- = - +t

 

 

 

Vo'3 ---------- t - +t

 

 

 

[E> D ' . -------- I - +t

 

 

PIN NAMES

 

 

 

 

GD ~'s ------- + - H

 

 

 

IT> D '6 --------- 7 -- H

 

 

 

~ D', -------- ++1

 

 

 

0> D'B ---------- ' -- +i

DOsIE>

 

 

IE> Cl R ----- 4

 

8-24

AFN-00731 A-o,

Page 285
Image 285
Intel mcs-48 manual PIN Configuration Logic Diagram, IT os, GD ~s ------- + H, DB ---------- -- +i