Intel mcs-48 manual ~O ~ ~

8259A

INTERRUPT SEQUENCE OUTPUTS

MCS·80/85SYSTEM

This sequence is timed by three INTA pulses. During the first iiifi'Apulse the CALL opcode is enabled onto the

data bus.						-
	Content of First Interrupt
		Vector Byte
D7	D8	D5	D4	D3	D2	Dl	DO

During the third INTApuise the higher address of the appropriate service routine, which was programmed as byte 2 of the initialization sequence (As - A 1sl, is enabled onto the bus.

Content of Third Interrupt

Vector Byte

07	06	05	D4	03	02	01	DO
A15	A14	A13	A12	All	Al0	A9	AS

CALLCODE ~1_l 0 0____________0 l~1

During the second INTA pulse the lower address of the appropriate service routine is enabled onto the data bus. When Interval =4 bits A5-A7 are programmed, while Ao- A4 are automatically inserted by the 8259A. When Inter· val =8 only A6 and A7 are programmed, while Ao-A5 are automatically inserted.

Content of Second Interrupt

Vector Byte

IR				Intervll-4
	D7	D8	D5	04	D3	02	Dl	DO
7	A7	A6	A5	1	1	1	0	0
6	A7	A6	A5	1	1	0	0	0
5	A7	A6	A5	1	0	1	0	0
4	A7	A6	A5	1	0	0	0	0
3	A7	A6	A5	0	1	1	0	0
2	A7	A6	A5	0	1	0	0	0
1	A7	A6	A5	0	0	1	0	0
0	A7	A6	A5	0	0	0	0	0
IA				Interval =8
	o7	o_6	D_5____o_4		o_3	D_2_~_0_1__~0~~_

7~~____A~6~____~___~__~___~O~__~O____O~

6A7 __A~6_____~__~__~O__~O:____~O____~

~~~A-7	----	A~6	--------	0~----		~--~O	----O~--	~O~
4	A7	A6		0		0	0	0
c --------------	A7	A6	0		1	0	0
3								o.~
2	A7	A6	0	1	0	0	0	0
1--1__ ~7__~6___~__Cl---					-------- ------		~--~-.-
					___ ~____O"____~ __~
o	A7	A6	0	0	0	0	0	0

MCS·8SSYSTEM

MCS·86 mode is similar to MCS·80 mode except that only two Interrupt Acknowledge cycles are issued by the processor and no CALL opcode is sent to the proc· essor. The first interrupt acknowledge cycle is similar to that of MCS-80/85systems in that the 8259A uses it to internally freeze the state of the interrupts for priority resoiuiion ana as a master it issues the interrupt code on the cascade lines at the end of the INTA pulse. On this first cycle it does not issue any data to the proc- essor and leaves its data bus buffers disabled. On the second interrupt acknowledge cycle in MCS·86 mode the master (or slave if so programmed) will send a byte of data to the processor with the acknowledged inter· rupt code composed as follows (note the state of the ADI mode control is ignored and A5-All are unused in MCS-86 mode):

Content of Interrupt Vector Byte

for MCS·86System Mode

	07	08	05	04	03	02	01	00
IR7	A15	A14	A13	A12	All	1	1	1
IR6	A15	A14	A13	A12	All	1	1	0
IR5	A15	A14	A13	A12	All	1	0	1
IR4	A15	A14	A13	A12	All	1	0	0
IR3	'115	A14	A13	A12	Al_~		1	1
IR2	A15	A14	A13	A12	'Ill	0	1	0
IRI	A15	A14	A13	A12	All	0	0	1
IRO	A15	A14	A13	A12	All	0	0	0
				~ ___ L....-- __				~_

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