Support Information
M9328MX21ADSE User’s Manual, Rev. A
Freescale Semiconductor 3-7
Figure 3-2. CPU to Base Board PX2/PY2 Connector Pin AssignmentsPX2
SD1_D3 1 • •2VCC
SD1_D2 3 • •4 SD1_CMD
SD1_D1 5 • •6 SD1_CLK
SD1_D0 7 • •8VCC
SD2_CLK 9 • •10 SD2_CMD
SD2_D3 11 • •12 SD2_D2
SD2_D1 13 • •14 SD2_D0
CSI_HSYNC 15 • •16 CSI_VSYNC
CSI_PIXCLK 17 • •18 CSI_MCLK
CSI_D7 19 • •20 CSI_D6
CSI_D5 21 • •22 CSI_D4
CSI_D3 23 • •24 CSI_D2
CSI_D1 25 • •26 CSI_D0
I2C_CLK 27 • •28 IS2_DATA
SSI3_CLK 29 • •30 SSI3_TXD
SSI3_RXD 31 • •32 SSI3_FS
SSI2_CLK 33 • •34 SSI2_TXD
SSI2_RXD 35 • •36 SSI2_FS
SSI1_CLK 37 • •38 SSI1_TXD
SSI1_RXD 39 • •40 SSI1_FS
SAP_CLK 41 • •42 SAP_RXD
SAP_FS 43 • •44 SAP_TXD
CSPI1_MOSI 45 • •46 CSPI1_MISO
CSPI1_SCLK 47 • •48 CSPI1_SS0
CSPI1_SS1 49 • •50 CSPI1_SS2
CSPI1_RDY 51 • •52 VCC
CSPI2_MOSI 53 • •54 CSPI2_MISO
CSPI2_SCLK 55 • •56 CSPI2_SS0
CSPI2_SS1 57 • •58 CSPI2_SS2
P5V 59 • •60 P5V
VCC 61 • •62 CPU_BD_ID0
CPU_BD_ID7 63 • •64 CPU_BD_ID1
CPU_BD_ID6 65 • •66 CPU_BD_ID2
CPU_BD_ID5 67 • •68 CPU_BD_ID3
CPU_BD_ID4 69 • •70 VCC
KP_COL5 71 • •72 KP_ROW5
KP_COL4 73 • •74 KP_ROW4
KP_COL3 75 • •76 KP_ROW3
KP_COL2 77 • •78 KP_ROW2
KP_COL1 79 • •80 KP_ROW1
KP_COL0 81 • •82 KP_ROW0
B_DQM0_EB0_B 83 • •84 B_DQM1_EB1_B
B_DQM2_EB2_B 85 • •86 TP21
B_A4 87 • •88 B_A5
B_A6 89 • •90 B_A7
B_A8 91 • •92 B_A9
B_A10 93 • •94 B_A11
B_A12 95 • •96 B_A13
B_A14 97 • •98 B_A15
B_A16 99 • •100 B_A17
B_A18 101 • •102 B_A19
B_D16 103 • •104 B_D17
B_D18 105 • •106 B_D19
B_D20 107 • •108 B_D21
B_D22 109 • •110 B_D23
B_D24 111 • •112 B_D25
B_D26 113 • •114 B_D27
B_D28 115 • •116 B_D29
B_D30 117 • •118 B_D31
RESET_SW 119 • •120 GND