Support Information
Table 3-8. Multi-ICE Connector P20 (on the CPU) Signal Descriptions
Pin(s) | Signal | Description |
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|
|
1, 2 | VCC | +3.0 VDC power |
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|
|
3 | TRST_B | TARGET RESET — Active low output signal that resets the target |
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|
|
4, 6, 8, 10, 12, | GND | GROUND |
14, 16, 18, 20 |
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|
|
|
|
5 | TDI | TEST DATA INPUT — Serial data output line, sampled on the rising edge of the TCK signal |
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|
|
7 | TMS | TEST MODE SELECT – Output signal that sequences the target’s JTAG state machine, |
|
| sampled on the rising edge of the TCK signal |
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|
|
9 | TCK | TEST CLOCK — Output timing signal, for synchronizing test logic and control register |
|
| access |
11 | RTCK | RETURN CLOCK |
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|
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13 | TDO | JTAG TEST DATA OUTPUT — Serial data input from the target |
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|
|
15 | RESET_IN_B | RESET IN — Active low reset signal to the processor |
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|
|
17, 19 | NC | NO CONNECTION |
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|
|
3.6Ethernet Connector
Connector P9 is the
1
Figure 3-9. Ethernet Connector P9 Pin Numbers
Table 3-9. Ethernet Connector P9 Signal Descriptions
Pin(s) | Signal | Description |
|
|
|
1 | TPO+ | DIFFERENTIAL OUTPUT PLUS |
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|
|
2 | TPO- | DIFFERENTIAL OUTPUT MINUS |
|
|
|
3 | TPI+ | DIFFERENTIAL INPUT PLUS |
|
|
|
4, 5, 7, 8 | NC | NO CONNECTION |
|
|
|
6 | TPI- | DIFFERENTIAL INPUT MINUS |
|
|
|
| M9328MX21ADSE User’s Manual, Rev. A |
Freescale Semiconductor |
