Table 5.16 Ultra DMA data burst timing requirements (2 of 2)
NAME | MODE 0 | MODE 1 | MODE 2 | COMMENT | |||
| (in ns) | (in ns) | (in ns) |
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| MIN | MAX | MIN | MAX | MIN | MAX |
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tIORDYZ |
| 20 |
| 20 |
| 20 | |
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| released |
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tZIORDY | 0 |
| 0 |
| 0 |
| Minimum time device shall wait before |
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| driving IORDY |
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tACK | 20 |
| 20 |
| 20 |
| Setup and hold times for DMACK- (before |
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| assertion or negation) |
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tSS | 50 |
| 50 |
| 50 |
| Time from STROBE edge to negation of |
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| DMARQ or assertion of STOP (when |
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| sender terminates a burst) |
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Notes: |
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1)tUI, tMLI and tLI indicate sender
2)All timing parameters are measured at the connector of the device to which the parameter applies. For example, the sender shall stop generating STROBE edges tRFS after the negation of
3)All timing measurement switching points (low to high and high to low) are to be taken at 1.5 V.
5 - 86 |