| Table 5.6 Features register values and settable modes |
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Features Register | Drive operation mode |
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X‘02’ | Enables the write cache function. |
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X‘03’ | Specifies the transfer mode. Supports PIO mode 4, single word DMA mode |
| 2, and multiword DMA mode regardless of Sector Count register contents. |
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X‘55’ | Disables read cache function. |
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X‘66’ | Disables the reverting to |
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X‘82’ | Disables the write cache function. |
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X‘AA’ | Enables the read cache function. |
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X‘BB’ | Specifies the transfer of |
| commands. |
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X‘CC’ | Enables the reverting to |
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At
At command issuance (I/O registers setting contents)
1F7H(CM) | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | ||
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1F6H(DH) | × | × | × |
| DV |
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| xx |
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1F5H(CH) |
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| xx |
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1F4H(CL) |
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| xx |
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1F3H(SN) |
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| xx |
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1F2H(SC) |
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| xx or transfer mode |
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1F1H(FR) |
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| [See Table 5.6] |
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At command completion (I/O registers contents to be read)
1F7H(ST) |
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| Status information |
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1F6H(DH) | × | × | × |
| DV |
| xx |
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1F5H(CH) |
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| xx |
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1F4H(CL) |
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| xx |
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1F3H(SN) |
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| xx |
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1F2H(SC) |
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| xx |
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1F1H(ER) |
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| Error information |
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5 - 34 |