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MPC3045AH, MPC3065AH
manual
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Models:
MPC3045AH
MPC3065AH
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3
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185 pages
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Specification
Install
MPC30xxAH Block diagram
PR4 signal transfer
Factory default setting
Dimension
drives configuration
Reset
Diagnostic code
Command block registers
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Contents
MPC3045AH MPC3065AH Disk Drives Product Manual
Revision Record
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Chapter
Preface
Conventions for Alert Messages
Liability Exception
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Contents
Interface
Theory of Device Operation
Page
Operations
Figures
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Tables
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Device Overview
Features Functions and performance
Interface
Adaptability
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Device Specifications Specifications summary
Specifications
MPC3045AH MPC3065AH
Model and product number
Model names and product numbers
MPC3045AH
Current and power dissipation
Current fluctuation Typ. when power is turned on
Drive Ready
Acoustic noise specification
Shock and vibration specification
Error Rate
Disk drive outerview
Device Configuration System Configuration
Configuration of disk media heads
2 1 drive connection
System Configuration ATA interface
3 2 drives connection
2 drives configuration
Dimensions Mounting Cable Connections Jumper Settings
Installation Conditions
Dimensions
Orientation
PCA
Limitation of side-mounting
Page
Service area
ATA
Cable Connections Device connector
Device connection
Cable connector specifications
Specters Strip
AMP
Power supply connector CN1
+12V Return +5V Return
CN1
11 Factory default setting Jumper configuration
Factory default setting
14 Example 1 of Cable Select
13 Jumper setting of Cable Select
408
Disk
Outline
Head
Actuator
Air filter
Circuit Configuration
MPC30xxAH Block diagram
Power-on Sequence
Power-on operation sequence
Self-calibration contents
Command processing during self-calibration
Self-calibration execution timechart
Read/write preamplifier PreAMP
Write circuit
Write precompensation algorithm
Read/write circuit block diagram
Read circuit
Frequency characteristic of programmable filter
PR4 signal transfer
Time base generator circuit
Write clock frequency and transfer rate of each zone
Servo control circuit
Physical sector servo configuration on disk surface
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Data-surface servo format
Servo frame format
PAD
Actuator motor control
Spindle motor control
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Interface
Physical Interface Interface signals
Intrq Pdiag DA1 DA2 DA0
Signal assignment on the connector
Signal assignment on the interface connector
Reset
Intrq
Dior
Hdmardy
Hstrobe
Ddmardy
Iordy
1 I/O registers
DA2 DA1 DA0
I/O registers
Icrc UNC Idnf Abrt TK0NF Amnf
Command block registers
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DEV HS3 HS2 HS1 HS0
BSY Drdy DSC DRQ ERR
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Srst
Control block registers
Command code and parameters 1
Command code and parameters
Command code and parameters 2
Command descriptions
LBA
LBA LSB
1F2 HSC Transfer sector count 1F1 HFR = 0 or C141-E056-01EN
Read Multiple XC4
BSY Drdy Intrq DRQ
Execution example of Read Multiple command
1F2 HSC Transfer sector count 1F1 HFR = 0 or C141-E056-01EN
LBA
LBA
Write Multiple XC5
LBA LSB
Write Verify X3C
LBA
1F4 HCL Cylinder No. LSB / LBA 1F3 HSN Sector No
Identify Device XEC
Initialize Device Parameters
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Information to be read by Identify Device command 1
Information to be read by Identify Device command 2
Information to be read by Identify Device command 3
Identify Device DMA XEE
SET Features XEF
‘CC’
Features register values and settable modes
‘AA’
‘BB’
SET Multiple Mode XC6
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Diagnostic code
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LBA
LBA
Write Buffer XE8
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XFF
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’DA’
Features Register values subcommands and functions
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1FE 1FF
Format of device attribute value data
10 Format of insurance failure threshold value data
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11 Contents of security password
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12 Contents of Security SET Password data
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14 Command code and parameters
Error posting
∙ Execute Device Diagnostic ∙ Initialize Device Parameters
Data transferring commands from device to host
∙ Identify Device ∙ Read Sectors ∙ Read Long ∙ Read Buffer
IOR
BSY
Drdy DRQ Intrq
DRQ Intrq
BSY Drdy DRQ Intrq
Write Sectors command protocol
BSY Drdy Intrq
Commands without data transfer
∙ Read DMA ∙ Write DMA ∙ Identify Device DMA
Other commands
DMA data transfer commands
∙ Read Multiple ∙ Sleep ∙ Write Multiple
IOW
DRQ Dmarq Dmack
Ultra DMA feature set Overview
Phases of operation
Data in transfer
Pausing an Ultra DMA data in burst
Terminating an Ultra DMA data in burst
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Data out transfer
Pausing an Ultra DMA data out burst
Terminating an Ultra DMA data out burst
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Ultra DMA CRC rules
DIOW-STOP
Series termination required for Ultra DMA
15 Recommended series termination for Ultra DMA
DIOR-HDMARDY-HSTROBE
DIOR-/DIOW
Timing PIO data transfer
Dmarq Dmack DIOR-/DIOW
Multiword data transfer
10 Initiating an Ultra DMA data in burst
Ultra DMA data transfer
Dmardy
Name Mode Comment MIN MAX
16 Ultra DMA data burst timing requirements 2
11 Sustained Ultra DMA data in burst
Sustained Ultra DMA data in burst
12 Host pausing an Ultra DMA data in burst
Host pausing an Ultra DMA data in burst
13 Device terminating an Ultra DMA data in burst
Device terminating an Ultra DMA data in burst
14 Host terminating an Ultra DMA data in burst
Host terminating an Ultra DMA data in burst
15 Initiating an Ultra DMA data out burst
16 Sustained Ultra DMA data out burst
Sustained Ultra DMA data out burst
17 Device pausing an Ultra DMA data out burst
Device pausing an Ultra DMA data out burst
18 Host terminating an Ultra DMA data out burst
Host terminating an Ultra DMA data out burst
19 Device terminating an Ultra DMA data out burst
Power-on and reset
BSY Dasp
Pdiag Dasp
Operations
Response to power-on
Response to hardware reset
Response to software reset
Response to diagnostic command
MPC3065AH MPC3045AH
Default parameters
Logical address
Address translation example in CHS mode
Power save mode
Address translation example in LBA mode Power Save
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Power commands
Alternating defective sectors
Spare area
Track slip processing
SP SP
Automatic Alternate assignment
10 Data buffer configuration
Data buffer configuration
Caching operation
∙ Read Sector S ∙ Read Multiple ∙ Read DMA
∙ Read Sectors ∙ Read DMA ∙ Read Multiple
Usage of read segment
HAP
DAP
Mis-hit data Empty data
Read-ahead data
HAP set to hit position for data transfer
Partially hit data Lack data
Requested data to be transferred
Write Cache
∙ Write Sectors ∙ Write Multiple ∙ Write DMA
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