5.3.2Command descriptions
The contents of the I/O registers to be necessary for issuing a command and the example indication of the I/O registers at command completion are shown as following in this subsection.
Example: READ SECTOR(S)
At command issuance (I/O registers setting contents)
Bit | 7 | 6 | 5 | 4 |
| 3 | 2 |
| 1 |
| 0 |
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1F7H(CM) | 0 | 0 | 1 | 0 | 0 | 0 |
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1F6H(DH) | × | L | × | DV |
| Head No. / LBA [MSB] | |||||
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1F5H(CH) |
| Start cylinder address [MSB] | / LBA |
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1F4H(CL) |
| Start cylinder address [LSB] / LBA |
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1F3H(SN) |
| Start sector No. |
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1F2H(SC) |
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| Transfer sector count |
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1F1H(FR) |
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| xx |
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At command completion (I/O registers contents to be read)
Bit | 7 | 6 | 5 |
| 4 | 3 |
| 2 |
| 1 |
| 0 |
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1F7H(ST) |
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| Status information |
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1F6H(DH) | × | L | × |
| DV | End Head No. / LBA [MSB] | |||||||
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1F5H(CH) |
| End cylinder address [MSB] / LBA |
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1F4H(CL) |
| End cylinder address [LSB] / LBA |
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1F3H(SN) |
| End sector No. |
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1F2H(SC) |
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| X‘00’ |
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1F1H(ER) |
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| Error information |
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CM: Command register |
| FR: Features register |
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DH: Device/Head register | ST: Status register |
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CH: Cylinder High register | ER: Error register |
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CL: Cylinder Low register | L: LBA (logical block address) setting bit | ||||||||||||
SN: Sector Number register | DV: Device address. bit |
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SC: Sector Count register | x, xx: Do not care (no necessary to set) | ||||||||||||
5 - 16 |
