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Fujitsu MPD3XXXAT manual Series termination required for Ultra DMA

Models: MPD3XXXAT

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5.5.6Series termination required for Ultra DMA

I)The CRC generator polynomial is : G (X) = X16 + X12 + X5 + 1.

Note: Since no bit clock is available, the recommended approach for calculating CRC is to use a word clock derived from the bus strobe. The combinational logic shall then be equivalent to shifting sixteen bits serially through the generator polynominal where DD0 is shifted in first and DD15 is shifted in last.

5.5.6Series termination required for Ultra DMA

Series termination resistors are required at both the host and the device for operation in any of the Ultra DMA Modes. The following table describes recommended values for series termination at the host and the device.

Table 5.15 Recommended series termination for Ultra DMA

Signal	Host Termination	Device Termination

DIOR-:HDMARDY-:HSTROBE	33 ohm	120 ohm A.I.*1

DIOW-:STOP	33 ohm	82 ohm

CS0-, CS1-	33 ohm	82 ohm

DA0, DA1, DA2	33 ohm	82 ohm

DMACK-	33 ohm	82 ohm

DD15 through DD0	33 ohm	120 ohm A.I.*1

DMARQ	82 ohm	22 ohm

INTRQ	82 ohm	22 ohm

IORDY:DDMARDY-:DSTROBE	82 ohm	22 ohm

Note: Only those signals requiring termination are listed in this table. If a signal is not listed, series termination is not required for operation in an Ultra DMA Mode. For signals also requiring a pull-up or pull-down resistor at the host see Figure 5.7.

*1: “A.I.” means an Active Inductance.

Figure 5.7 Ultra DMA termination with pull-up or pull-down

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C141-E069-02EN

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Fujitsu MPD3XXXAT manual Series termination required for Ultra DMA, 15 Recommended series termination for Ultra DMA

Contents

C141-E069-02EN MPD3xxxAT DISK DRIVES PRODUCT MANUALEdition Revised contentsThe contents of this manual is subject to REVISION RECORDThis page is intentionally left blank Chapter DEVICE CONFIGURATIONINSTALLATION CONDITIONS PREFACEConventions for Alert Messages C141-E069-02EN LIABILITY EXCEPTIONThis page is intentionally left blank CHAPTER CONTENTSCHAPTER CHAPTERJumper configuration Jumper SettingsLocation of setting jumpers Factory default settingCommand descriptions Command block registersHost Commands Command code and parametersResponse to power-on Device pausing an Ultra DMA data out burstPower-on and reset Device Response to the ResetFIGURES Multiword DMA data transfer timing mode Protocol for command abortWRITE SECTORS command protocol Protocol for the command execution without data transferTABLES This page is intentionally left blank 1.1 Features 1.1.1 Functions and performance 1.1 Features 1.2 Device Specifications 1.3 Power Requirements1.4 Environmental Specifications 1.5 Acoustic Noise 1.6 Shock and Vibration 1.7 Reliability 1.8 Error Rate1.1.3 Interface 1.1.2 Adaptability6 Write cache 5 Error correction and retry by ECCC141-E069-02EN C141-E069-02EN 1.2 Device Specifications 1.2.1 Specifications summarySpecifications Table 1.1 shows the specifications of the disk drive1.2.2 Model and product number 1.3 Power RequirementsTable 1.2 Model names and product numbers C141-E069-02EN Table 1.3 Current and power dissipationFigure 1.1 Current fluctuation Typ. when power is turned on 1.5 Acoustic Noise 1.4 Environmental SpecificationsEnvironmental specifications Table 1.5 Acoustic noise specification1.6 Shock and Vibration Table 1.6 Shock and vibration specification1.7 Reliability 1.9 Media Defects 1.8 Error RateFigure 2.1 Disk drive outerview CHAPTER 2 DEVICE CONFIGURATION2.1 Device Configuration 2.2 System Configuration 2.1 Device Configuration3 Spindle motor 1 DiskMPD3043AT 1 disk MPD3064AT, MPD3084AT 2 disks MPD3108AT, MPD3130AT 3 disks MPD3173AT 4 disks 2 Head2.2.2 1 drive connection 2.2 System Configuration 2.2.1 ATA interfaceFigure 2.2 1 drive system configuration 2.2.3 2 drives connection Figure 2.3 2 drives configurationC141-E069-02EN 3.1 Dimensions 3.2 Mounting 3.3 Cable Connections 3.4 Jumper Settings CHAPTER 3 INSTALLATION CONDITIONS3.1 Dimensions C141-E069-02EN Figure 3.1 DimensionsFigure 3.2 Orientation 3.2 MountingFigure 3.4 Mounting frame structure Figure 3.3 Limitation of side-mountingTable 3.1 Surface temperature measurement points and standard values Figure 3.5 Surface temperature measurement pointsFigure 3.6 Service area Power supply connector CN1 Mode Setting Pins ATA interface connector 3.3 Cable Connections 3.3.1 Device connectorFigure 3.7 Connector locations ∙ Power supply connector CN1 ∙ ATA interface connector CN1Figure 3.8 Cable connections 3.3.2 Cable connector specificationsCable connector specifications 3.3.3 Device connectionFigure 3.9 Power supply connector pins CN1 3.3.4 Power supply connector CN13.3.5 System configuration for Ultra DMA Cable configuration Figure 3.11 Cable type detection using CBLID- signal Host sensing the condition of the CBLID- signal Interface Connector 3.4 Jumper Settings 3.4.1 Location of setting jumpersFigure 3.13 Jumper location DC Power ConnectorFigure 3.14 Factory default setting 3.4.3 Jumper configuration 3.4.2 Factory default settingFigure 3.15 Jumper setting of master or slave device Figure 3.17 Example 1 of Cable Select Figure 3.16 Jumper setting of Cable SelectFigure 3.18 Example 2 of Cable Select Cable Select 3 Special jumper settings a 2.1 GB clip Limit capacity to 2.1 GBMaster Device Slave DeviceThis page is intentionally left blank 4.7 Servo Control 4.1 Outline 4.2 Subassemblies 4.3 Circuit Configuration4.4 Power-on sequence 4.5 Self-calibration 4.6 Read/write Circuit CHAPTER 4 THEORY OF DEVICE OPERATIONC141-E069-02EN 4.2.2 HeadMPD3108AT Model Figure 4.1 Head structureMPD3043AT Model MPD3064AT Model4.2.4 Actuator 4.2.3 Spindle4.2.5 Air filter 4.3 Circuit Configuration C141-E069-02EN Figure 4.2 MPD3xxxAT Block diagram4.4 Power-on Sequence Figure 4.3 Power-on operation sequence 4.5 Self-calibration 4.5.1 Self-calibration contents4.5.3 Command processing during self-calibration Table 4.1 Self-calibration execution timechart4.6.1 Read/write preamplifier PreAMP 4.6 Read/write Circuit4.6.2 Write circuit C141-E069-02EN Figure 4.4 Read/write circuit block diagram4.6.3 Read circuit Table 4.2 Write clock frequency and transfer rate of each zone 4.6.4 Time base generator circuit4.7 Servo Control 4.7.1 Servo control circuit Figure 4.5 Block diagram of servo control circuitServo frame 96 servo frames per revolution Figure 4.6 Physical sector servo configuration on disk surface4 D/A converter DAC 5 Power amplifier2 Servo burst capture circuit 3 A/D converter ADC4.7.3 Servo frame format 4.7.2 Data-surface servo formatFigure 4.7 Servo frame format 4.7.4 Actuator motor control 4.7.5 Spindle motor control 3 Stable rotation mode 2 Acceleration modeC141-E069-02EN 5.4 Command Protocol 5.5 Ultra DMA feature set 5.6 Timing 5.1 Physical Interface 5.2 Logical Interface 5.3 Host CommandsCHAPTER 5 INTERFACE C141-E069-02EN 5.1 Physical Interface 5.1.1 Interface signalsTable 5.1 Interface signals Table 5.1 shows the interface signalsTable 5.2 Signal assignment on the interface connector 5.1.2 Signal assignment on the connectorsignal device is ready to receive Ultra DMA data out bursts. The device may 5.2.1 I/O registers 5.2 Logical InterfaceTable 5.3 I/O registers 5.2.2 Command block registers X80 Device 1 slave device Failed Diagnostic code X01 No Error Detected X02 HDC Register Compare ErrorX03 Data Buffer Compare Error X05 ROM Sum Check Error 3 Features register X1F1Bit 2 HS2 CHS mode head address 3 22. LBA bit The contents of this register indicate the device and the head numberBit 7 Unused Bit 6 L. 0 for CHS mode and 1 for LBA mode Bit 5 Unused Bit 3 HS3 CHS mode head address 3 23. LBA bitDRDY 9 Status register X1F7C141-E069-02EN C141-E069-02EN 10 Command register X1F7Always Always5.2.3 Control block registers 5.3 Host CommandsTable 5.4 Command code and parameters 1 of 5.3.1 Command code and parametersTable 5.4 Command code and parameters 2 of 5.3.2 Command descriptions 1F6 HDH At command issuance I/O registers setting contents1 READ SECTORS X20 or 1F7 HCMStatus information At command completion I/O registers contents to be readError information 1F7 HSTFigure 5.1 Execution example of READ MULTIPLE command 2 Ultra DMA transfer mode ∙ The data transfer starts at the timing of DMARQ signal assertionIn LBA mode 1 Multiword DMA transfer mode1F7 HST At command completion I/O registers contents to be readError information At command issuance I/O registers setting contents1F7 HST At command completion I/O registers contents to be readError information At command issuance I/O registers setting contentsStatus information At command completion I/O registers contents to be readError information 1F7 HST∙ The data transfer starts at the timing of DMARQ signal assertion At command issuance I/O registers setting contentsAt command completion I/O registers contents to be read Error informationR = 0 or At command completion I/O registers contents to be read 1 Multiword DMA transfer mode2 Ultra DMA transfer mode At command issuance I/O registers setting contentsAt command issuance I/O registers setting contents At command completion I/O registers contents to be readError information This command can be issued in the LBA mode10 SEEK X7x, x X0 to XF At command issuance I/O registers setting contentsAt command completion I/O registers contents to be read Error informationError Information In LBA modeAt command issuance I/O registers setting contents At command completion I/O registers contents to be read1F7HCM At command issuance I/O registers setting contentsAt command completion I/O registers contents to be read Error informationC141-E069-02EN Table 5.5 Information to be read by IDENTIFY DEVICE command 1 ofTable 5.5 Information to be read by IDENTIFY DEVICE command 2 of Table 5.5 Information to be read by IDENTIFY DEVICE command 3 of Table 5.5 Information to be read by IDENTIFY DEVICE command 4 of 14 SET FEATURES XEF At command issuance I/O registers setting contentsAt command completion I/O registers contents to be read Error informationTable 5.6 Features register values and settable modes Error information At command issuance I/O registers setting contentsxx or transfer mode At command completion I/O registers contents to be readError information 15 SET MULTIPLE MODE XC6At command issuance I/O registers setting contents At command completion I/O registers contents to be readWhen device 1 is not present Word 59 = 0000 The READ MULTIPLE and WRITE MULTIPLE commands aredisabled = 16 EXECUTE DEVICE DIAGNOSTICTable 5.7 Diagnostic code Error information The READ LONG command supports only single sector operationAt command issuance I/O registers setting contents R = 0 or At command completion I/O registers contents to be readAt command issuance I/O registers setting contents At command issuance I/O registers setting contentsR = 0 or At command completion I/O registers contents to be read Error informationAt command completion I/O registers contents to be read At command completion I/O registers contents to be readError information At command issuance I/O registers setting contentsPeriod of timer Point of timerDisable of timer At command issuance I/O registers setting contentsAt command completion I/O registers contents to be read At command completion I/O registers contents to be readError information At command issuance I/O registers setting contentsError information At command issuance I/O registers setting contentsPeriod of timer At command completion I/O registers contents to be readThis command is the only way to make the device enter the sleep mode At command issuance I/O registers setting contentsAt command completion I/O registers contents to be read Error informationThe host checks the power mode of the device with this command At command completion I/O registers contents to be readError information 27 CHECK POWER MODE X98 or XE51F7 HCM At command issuance I/O registers setting contentsAt command completion I/O registers contents to be read Error informationTable 5.8 Features Register values subcommands and functions Error information At command issuance I-O registers setting contentsSubcommand At command completion I-O registers setting contentsTable 5.9 Format of device attribute value data Table 5.10 Format of insurance failure threshold value data Number of power-on-power-off times Read error rateSeek error rate Power-on time∙ Insurance failure threshold ∙ Raw attribute value Raw attributes data is retained∙ Failure prediction capability flag Bits 2 to 15 Reserved bits ∙ Check sumError information NOTE - This command may take longer than 30 s to completeAt command issuance I/O registers setting contents At command completion I/O registers contents to be readTable 5.11 Contents of security password 1F7 HCM At command issuance I-O registers setting contentsAt command completion I-O registers setting contents Error information1F7 HCM At command issuance I-O registers setting contentsAt command completion I-O registers setting contents Error information∙ SECURITY SET PASSWORD ∙ SECURITY UNLOCK ∙ SECURITY DISABLE PASSWORD At command issuance I-O registers setting contentsAt command completion I-O registers setting contents Error informationAt command completion I-O registers setting contents SECURITY DISABLE PASSWORDSECURITY SET PASSWORD At command issuance I-O registers setting contentsoperation of the lock function Table 5.12 Contents of SECURITY SET PASSWORD dataTable 5.13 Relationship between combination of Identifier and Security level, and35 SECURITY UNLOCK F2h This command cancels LOCKED MODE At command issuance I-O registers setting contentsAt command completion I-O registers setting contents Error information1F7 HCM At command issuance I-O registers setting contentsAt command completion I-O registers setting contents Error informationAt command issuance I/O registers setting contents At command issuance I/O registers setting contentsAt command completion I/O registers contents to be read Error informationStatus information At command completion I/O registers contents to be readError information 1F7HSTTable 5.14 Command code and parameters 5.3.3 Error postingDRDY 5.4.1 Data transferring commands from device to host 5.4 Command ProtocolFigure 5.2 Read Sectors command protocol 5.4.2 Data transferring commands from host to device Figure 5.3 Protocol for command abortFigure 5.4 WRITE SECTORS command protocol Figure 5.5 Protocol for the command execution without data transfer 5.4.3 Commands without data transfer5.4.5 DMA data transfer commands 5.4.4 Other commandsFigure 5.6 Normal DMA data transfer 5.5 Ultra DMA feature set 5.5.1 Overview 5.5.3 Ultra DMA data in commands 5.5.2 Phases of operation5.5.3.1 Initiating an Ultra DMA data in burst 5.5.3.2 The data in transfer 5.5.3.3 Pausing an Ultra DMA data in burst5.5.3.4 Terminating an Ultra DMA data in burst C141-E069-02EN b Host terminating an Ultra DMA data in burst5.5.4.1 Initiating an Ultra DMA data out burst 5.5.4 Ultra DMA data out commands5.5.4.2 The data out transfer 5.5.4.3 Pausing an Ultra DMA data out burst5.5.4.4 Terminating an Ultra DMA data out burst C141-E069-02EN b Device terminating an Ultra DMA data out burst5.5.5 Ultra DMA CRC rules Table 5.15 Recommended series termination for Ultra DMA 5.5.6 Series termination required for Ultra DMAFigure 5.7 Ultra DMA termination with pull-up or pull-down Figure 5.8 PIO data transfer timing 5.6 Timing 5.6.1 PIO data transfer5.6.2 Multiword data transfer Figure 5.9 Multiword DMA data transfer timing mode5.6.3.1 Initiating an Ultra DMA data in burst 5.6.3 Ultra DMA data transferFigure 5.10 Initiating an Ultra DMA data in burst Table 5.16 Ultra DMA data burst timing requirements 1 of 5.6.3.2 Ultra DMA data burst timing requirementsUIMLI Table 5.16 Ultra DMA data burst timing requirements 2 oftZIORDY tACKFigure 5.11 Sustained Ultra DMA data in burst 5.6.3.3 Sustained Ultra DMA data in burstFigure 5.12 Host pausing an Ultra DMA data in burst 5.6.3.4 Host pausing an Ultra DMA data in burstFigure 5.13 Device terminating an Ultra DMA data in burst 5.6.3.5 Device terminating an Ultra DMA data in burstFigure 5.14 Host terminating an Ultra DMA data in burst 5.6.3.6 Host terminating an Ultra DMA data in burstFigure 5.15 Initiating an Ultra DMA data out burst 5.6.3.7 Initiating an Ultra DMA data out burstFigure 5.16 Sustained Ultra DMA data out burst 5.6.3.8 Sustained Ultra DMA data out burstFigure 5.17 Device pausing an Ultra DMA data out burst 5.6.3.9 Device pausing an Ultra DMA data out burstFigure 5.18 Host terminating an Ultra DMA data out burst 5.6.3.10 Host terminating an Ultra DMA data out burstFigure 5.19 Device terminating an Ultra DMA data out burst 5.6.3.11 Device terminating an Ultra DMA data in burstFigure 5.20 Power-on Reset Timing 5.6.4 Power-on and resetThis page is intentionally left blank CHAPTER 6 OPERATIONS 6.1 Device Response to the Reset 6.2 Address Translation6.3 Power Save 6.4 Defect Management 6.5 Read-Ahead Cache 6.6 Write Cache 6.1 Device Response to the ResetFigure 6.1 Response to power-on 6.1.1 Response to power-onFigure 6.2 Response to hardware reset 6.1.2 Response to hardware resetFigure 6.3 Response to software reset 6.1.3 Response to software resetFigure 6.4 Response to diagnostic command 6.1.4 Response to diagnostic commandMPD3043AT 6.2.1 Default parametersTable 6.1 Default parameters 6.2 Address Translation6.2.2 Logical address Figure 6.5 Address translation example in CHS mode6.3.1 Power save mode Figure 6.6 Address translation example in LBA mode 6.3 Power Save∙ A command other than power commands is issued 1 Active modeA device enters the active mode under the following conditions ∙ Power-on sequence is completed6.4 Defect Management 6.3.2 Power commandsDefective 6.4.1 Spare area6.4.2 Alternating defective sectors Figure 6.7 Sector slip processingunused Figure 6.8 Alternate cylinder assignmentFigure 6.9 Data buffer configuration 6.5.1 Data buffer configuration6.5 Read-Ahead Cache 6.5.2 Caching operation 6.5.3 Usage of read segment Empty data a. Sequential command just after non-sequential command3 Sequential read Mis-hit dataHit data b. Sequential hitHAP Completion of transferring requested data Read-ahead dataHAP set to hit position for data transfer Last position at previous read commandDAP Last position at previous read command 3 Full hit hit allstopped 6.6 Write Cache When the write cache function is enabled, the transferred data from the host by the WRITE SECTORS is not completely written on the disk medium at the time that the interrupt of command complete is generated. When the unrecoverable error occurs during the write operation, the command execution is stopped. Then, when the drive receives the next command, it generates an interrupt of abnormal end. However an interrupt of abnormal end is not generated when a write automatic assignment succeeds. However, since the host may issue several write commands before the drive generates an interrupt of abnormal end, the host cannot recognize that the occurred error is for which command generally. Therefore, it is very hard to retry the unrecoverable write error for the host in the write cache operation generally. So, take care to use the write cache function I, Place des Etas-Unis, SILIC 310, 94588 Rungis Cedex, FRANCE Reader Comment Form FUJITSU LIMITED