Fujitsu MPD3XXXAT manual Read circuit

4.6.3Read circuit

The head read signal from the PreAMP is regulated by the automatic gain control (AGC) circuit. Then the output is converted into the sampled read data pulse by the programmable filter circuit and the adaptive equalizer circuit. This clock signal is converted into the NRZ data by the 16/17 GCR decoder circuit based on the read data maximum-likelihood-detected by the Viterbi detection circuit, then is sent to the HDC.

(1)AGC circuit

The AGC circuit automatically regulates the output amplitude to a constant value even when the input amplitude level fluctuates. The AGC amplifier output is maintained at a constant level even when the head output fluctuates due to the head characteristics or outer/inner head positions.

(2)Programmable filter

The programmable filter circuit has a low-pass filter function that eliminates unnecessary high frequency noise component and a high frequency boost-up function that equalizes the waveform of the read signal.

Cut-off frequency of the low-pass filter and boost-up gain are controlled from each DAC circuit in read channel by an instruction of the serial data signal from MPU (M1). The MPU optimizes the cut-off frequency and boost-up gain according to the transfer frequency of each zone.

(3)Adaptive equalizer circuit

This circuit is 5-tap sampled analog transversal filter circuit that cosine-equalizes the head read signal to the Extended Partial Response Class 4 (EPR4) waveform.

(4)Viterbi detection circuit

The sample hold waveform output from the adaptive equalizer circuit is sent to the Viterbi detection circuit. The Viterbi detection circuit demodulates data according to the survivor path sequence.

(5)Data separator circuit

The data separator circuit generates clocks in synchronization with the output of the adaptive equalizer circuit. To write data, the VFO circuit generates clocks in synchronization with the clock signals from a synthesizer.

(6)16/17 GCR decoder

This circuit converts the 17-bits read data into the 16-bits NRZ data.

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