Dmardy | Fujitsu MPD3XXXAT manual

5.6.3.2 Ultra DMA data burst timing requirements

Table 5.16 Ultra DMA data burst timing requirements (1 of 2)

NAME	MODE 0		MODE 1		MODE 2		MODE 3		MODE 4		COMMENT
	(in ns)		(in ns)		(in ns)		(in ns)		(in ns)

	MIN	MAX	MIN	MAX	MIN	MAX	MIN	MAX	MIN	MAX	(see Notes 1 and 2)

t2CYCTYP	240		160		120		90		60		Typical sustained average two cycle
											time

tCYC	112		73		54		39		25		Cycle time allowing for asymmetry
											and clock variations (from STROBE
											edge to STROBE edge)

t2CYC	230		154		115		86		57		Two cycle time allowing for clock
											variations (from rising edge to next
											rising edge or from falling edge to
											next falling edge of STROBE)

tDS	15		10		7		7		5		Data setup time (at recipient)
											(see Note 4)

tDH	5		5		5		5		5		Data hold time (at recipient)
											(see Note 4)

tDVS	70		48		30		20		6		Data valid setup time at sender (from
											data valid until STROBE edge)
											(see Note 5)

tDVH	6		6		6		6		6		Data valid hold time at sender (from
											STROBE edge until data may
											become invalid) (see Note 5)

tFS	0	230	0	200	0	170	0	130	0	120	First STROBE time (for device to
											first negate DSTROBE from STOP
											during a data in burst)

tLI	0	150	0	150	0	150	0	100	0	100	Limited interlock time (see Note 3)

tMLI	20		20		20		20		20		Interlock time with minimum
											(see Note 3)

tUI	0		0		0		0		0		Unlimited interlock time (see Note 3)

tAZ		10		10		10		10		10	Maximum time allowed for output
											drivers to release (from asserted or
											negated)

tZAH	20		20		20		20		20		Minimum delay time required for
											output

tZAD	0		0		0		0		0		Drivers to assert or negate (from
											released)

tENV	20	70	20	70	20	70	20	55	20	55	Envelope time (from DMACK- to
											STOP and HDMARDY- during data
											in burst initiation and from DMACK
											to STOP during data out burst
											initiation)

tSR		50		30		20		NA		NA	STROBE-to-DMARDY-time (if
											DMARDY- is negated before this long
											after STROBE edge, the recipient shall
											receive no more than one additional
											data word)

tRFS		75		70		60		60		60	Ready-to-final-STROBE time (no
											STROBE edges shall be sent this
											long after negation of DMARDY-)

tRP	160		125		100		100		100		Ready-to-pause time (that recipient
											shall wait to pause after negating
											DMARDY-)

tIORDYZ		20		20		20		20		20	Maximum time before releasing
											IORDY

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C141-E069-02EN

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Fujitsu MPD3XXXAT manual Dmardy

Contents

Disk Drives Product Manual Revision Record This page is intentionally left blank Chapter Preface Conventions for Alert Messages Liability Exception This page is intentionally left blank Contents Interface Theory of Device OperationPage Operations Figures Page Tables This page is intentionally left blank Device Overview Features Functions and performance Interface AdaptabilityPage Specifications Device Specifications Specifications summary Model names and product numbers Model and product number Current and power dissipation +5VDC Current fluctuation Typ. when power is turned on Acoustic noise specification Shock and vibration specification Error Rate Disk drive outerview Device Configuration System ConfigurationPage 2 1 drive connection System Configuration ATA interface C141-E069-02EN Dimensions Mounting Cable Connections Jumper Settings Installation Conditions Dimensions Orientation PCA Limitation of side-mountingPage Service area Connector locations Cable Connections Device connector Device connection Cable connector specificationsAMP +12V Return +5V Return Power supply connector CN1 Cable configuration Host detected CBLID- above VIH 13 Jumper location Jumper Settings Location of setting jumpers 14 Factory default setting Jumper configuration Factory default setting 17 Example 1 of Cable Select 16 Jumper setting of Cable Select 092 This page is intentionally left blank Disk Outline Head Head structure Air filter SpindleActuator Circuit Configuration MPD3xxxAT Block diagram Power-on Sequence Power-on operation sequence Self-calibration contents Command processing during self-calibration Self-calibration execution timechart Write circuit Read/write preamplifier PreAMP Read/write circuit block diagram Read circuit Write clock frequency and transfer rate of each zone Time base generator circuit Servo control circuit Physical sector servo configuration on disk surface Page Servo frame format Data-surface servo format Data POS PAD Actuator motor control Spindle motor control Page Interface Physical Interface Interface signals Intrq PDIAG-, Cblid DA1 DA2 DA0 Signal assignment on the connectorSignal assignment on the interface connector Reset Intrq DiorHdmardy Hstrobe Ddmardy Iordy 1 I/O registers DA2 DA1 DA0 I/O registers Icrc UNC Idnf Abrt TK0NF Amnf Command block registersPage DEV HS3 HS2 HS1 HS0 BSY Drdy DSC DRQ ERR Page Srst Control block registers Command code and parameters 1 Command code and parameters Command code and parameters 2 LBA LSB Command descriptionsLBA 1F2 HSC Transfer sector count 1F1 HFR = 0 or C141-E069-02EN Read Multiple XC4 BSY Drdy Intrq DRQ Execution example of Read Multiple command 1F2 HSC Transfer sector count 1F1 HFR = 0 or C141-E069-02EN LBA LBA Write Multiple XC5 LBA LSB Write Verify X3C LBA 1F4 HCL Cylinder No. LSB / LBA 1F3 HSN Sector No Identify Device XEC Initialize Device ParametersPage Information to be read by Identify Device command 1 ‘3FFF’ Information to be read by Identify Device command 2MPD3043AT MPD3064AT MPD3084AT MPD3108AT MPD3130AT MPD3173AT Information to be read by Identify Device command 3 Information to be read by Identify Device command 4 Identify Device DMA XEE SET Features XEF ‘BB’ Features register values and settable modes‘AA’ ‘AB’Page SET Multiple Mode XC6 Execute Device Diagnostic Diagnostic code LBA LBA Write Buffer XE8 Page Page Page Page XFF Page ’DA’ Features Register values subcommands and functionsPage 1FE 1FF Format of device attribute value data 10 Format of insurance failure threshold value data Page Page Page 11 Contents of security password Page Page Page Page 12 Contents of Security SET Password data Page SET MAX Address F9 Read Native MAX Address F8 Page 14 Command code and parameters Error posting Data transferring commands from device to host ∙ Execute Device Diagnostic ∙ Initialize Device Parameters IOR BSYDrdy DRQ Intrq DRQ Intrq BSY Drdy DRQ Intrq Write Sectors command protocol BSY Drdy Intrq Commands without data transfer∙ SET MAX Address ∙ Read Native MAX Address ∙ Read DMA ∙ Write DMA Other commandsDMA data transfer commands ∙ Read Multiple ∙ Sleep ∙ Write Multiple IOW DRQ Dmarq Dmack Ultra DMA feature set Overview Phases of operation Data in transfer Pausing an Ultra DMA data in burst Terminating an Ultra DMA data in burst Page Page Data out transfer Pausing an Ultra DMA data out burst Terminating an Ultra DMA data out burst Page Ultra DMA CRC rules DIOW-STOP Series termination required for Ultra DMA15 Recommended series termination for Ultra DMA DIOR-HDMARDY-HSTROBE DIOR-/DIOW Timing PIO data transfer Dmarq Dmack DIOR-/DIOW Multiword data transfer 10 Initiating an Ultra DMA data in burst Ultra DMA data transfer Dmardy 16 Ultra DMA data burst timing requirements 2 11 Sustained Ultra DMA data in burst Sustained Ultra DMA data in burst 12 Host pausing an Ultra DMA data in burst Host pausing an Ultra DMA data in burst 13 Device terminating an Ultra DMA data in burst Device terminating an Ultra DMA data in burst 14 Host terminating an Ultra DMA data in burst Host terminating an Ultra DMA data in burst 15 Initiating an Ultra DMA data out burst 16 Sustained Ultra DMA data out burst Sustained Ultra DMA data out burst 17 Device pausing an Ultra DMA data out burst Device pausing an Ultra DMA data out burst 18 Host terminating an Ultra DMA data out burst Host terminating an Ultra DMA data out burst 19 Device terminating an Ultra DMA data out burst Pdiag Dasp Power-on and resetBSY Dasp This page is intentionally left blank Operations Pdiag Response to power-on Response to hardware reset Response to software reset Response to diagnostic command MPD3130AT MPD3173AT Default parameters Logical address Address translation example in CHS mode Power save mode Address translation example in LBA mode Power SavePage Power commands Alternating defective sectors Spare area Alternate cylinder assignment Data buffer configuration ∙ Write Sectors ∙ Write DMA ∙ Write Multiple Caching operation∙ Read Sector S ∙ Read Multiple ∙ Read DMA DAP Usage of read segmentHAP Mis-hit data Empty data Read-ahead data New read-ahead data Hit data HAP set to hit position for data transfer Partially hit data Lack data Write Cache ∙ Write Sectors ∙ Write Multiple ∙ Write DMA Fujitsu Canada INC Fujitsu Limited