Table 5.3 I/O registers
CS0– | CS1– | DA2 | DA1 | DA0 | I/O registers | Host I/O | ||
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Read operation | Write operation | address | ||||||
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Command block registers |
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1 | 0 | 0 | 0 | 0 | Data | Data | X'1F0' | |
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1 | 0 | 0 | 0 | 1 | Error Register | Features | X'1F1' | |
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1 | 0 | 0 | 1 | 0 | Sector Count | Sector Count | X'1F2' | |
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1 | 0 | 0 | 1 | 1 | Sector Number | Sector Number | X'1F3' | |
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1 | 0 | 1 | 0 | 0 | Cylinder Low | Cylinder Low | X'1F4' | |
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1 | 0 | 1 | 0 | 1 | Cylinder High | Cylinder High | X'1F5' | |
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1 | 0 | 1 | 1 | 0 | Device/Head | Device/Head | X'1F6' | |
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1 | 0 | 1 | 1 | 1 | Status | Command | X'1F7' | |
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1 | 1 | X | X | X | (Invalid) | (Invalid) | — | |
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Control block registers |
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0 | 1 | 1 | 1 | 0 | Alternate Status | Device Control | X'3F6' | |
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0 | 1 | 1 | 1 | 1 | — | — | X'3F7' | |
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Notes:
1.The Data register for read or write operation can be accessed by 16 bit data bus (DATA0 to DATA15).
2.The registers for read or write operation other than the Data registers can be accessed by 8 bit data bus (DATA0 to DATA7).
3.When reading the Drive Address register, bit 7 is
4.The LBA mode is specified, the Device/Head, Cylinder High, Cylinder Low, and Sector Number registers indicate LBA bits 27 to 24, 23 to 16, 15 to 8, and 7 to 0.
| 5 - 7 |
