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Fujitsu MPD3XXXAT manual 3 I/O registers

Models: MPD3XXXAT

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Table 5.3 I/O registers

	CS0–	CS1–	DA2	DA1	DA0	I/O registers		Host I/O
								Host I/O
						Read operation	Write operation	address
								address


	Command block registers

	1	0	0	0	0	Data	Data	X'1F0'

	1	0	0	0	1	Error Register	Features	X'1F1'

	1	0	0	1	0	Sector Count	Sector Count	X'1F2'

	1	0	0	1	1	Sector Number	Sector Number	X'1F3'

	1	0	1	0	0	Cylinder Low	Cylinder Low	X'1F4'

	1	0	1	0	1	Cylinder High	Cylinder High	X'1F5'

	1	0	1	1	0	Device/Head	Device/Head	X'1F6'

	1	0	1	1	1	Status	Command	X'1F7'

	1	1	X	X	X	(Invalid)	(Invalid)	—

	Control block registers

	0	1	1	1	0	Alternate Status	Device Control	X'3F6'

	0	1	1	1	1	—	—	X'3F7'

Notes:

1.The Data register for read or write operation can be accessed by 16 bit data bus (DATA0 to DATA15).

2.The registers for read or write operation other than the Data registers can be accessed by 8 bit data bus (DATA0 to DATA7).

3.When reading the Drive Address register, bit 7 is high-impedance state.

4.The LBA mode is specified, the Device/Head, Cylinder High, Cylinder Low, and Sector Number registers indicate LBA bits 27 to 24, 23 to 16, 15 to 8, and 7 to 0.

C141-E069-02EN

5 - 7

Image 74

Fujitsu MPD3XXXAT manual 3 I/O registers

Contents

MPD3xxxAT DISK DRIVES PRODUCT MANUAL C141-E069-02ENREVISION RECORD Revised contentsThe contents of this manual is subject to EditionThis page is intentionally left blank PREFACE DEVICE CONFIGURATIONINSTALLATION CONDITIONS ChapterConventions for Alert Messages LIABILITY EXCEPTION C141-E069-02ENThis page is intentionally left blank CHAPTER CONTENTSCHAPTER CHAPTERFactory default setting Jumper SettingsLocation of setting jumpers Jumper configurationCommand code and parameters Command block registersHost Commands Command descriptionsDevice Response to the Reset Device pausing an Ultra DMA data out burstPower-on and reset Response to power-onFIGURES Protocol for the command execution without data transfer Protocol for command abortWRITE SECTORS command protocol Multiword DMA data transfer timing modeTABLES This page is intentionally left blank 1.6 Shock and Vibration 1.7 Reliability 1.8 Error Rate 1.1 Features 1.2 Device Specifications 1.3 Power Requirements1.4 Environmental Specifications 1.5 Acoustic Noise 1.1 Features 1.1.1 Functions and performance1.1.2 Adaptability 1.1.3 InterfaceC141-E069-02EN 5 Error correction and retry by ECC6 Write cache Table 1.1 shows the specifications of the disk drive 1.2 Device Specifications 1.2.1 Specifications summarySpecifications C141-E069-02ENTable 1.2 Model names and product numbers 1.3 Power Requirements1.2.2 Model and product number Table 1.3 Current and power dissipation C141-E069-02ENFigure 1.1 Current fluctuation Typ. when power is turned on Table 1.5 Acoustic noise specification 1.4 Environmental SpecificationsEnvironmental specifications 1.5 Acoustic Noise1.7 Reliability Table 1.6 Shock and vibration specification1.6 Shock and Vibration 1.8 Error Rate 1.9 Media Defects2.1 Device Configuration CHAPTER 2 DEVICE CONFIGURATION2.1 Device Configuration 2.2 System Configuration Figure 2.1 Disk drive outerviewMPD3108AT, MPD3130AT 3 disks MPD3173AT 4 disks 2 Head 1 DiskMPD3043AT 1 disk MPD3064AT, MPD3084AT 2 disks 3 Spindle motorFigure 2.3 2 drives configuration 2.2 System Configuration 2.2.1 ATA interfaceFigure 2.2 1 drive system configuration 2.2.3 2 drives connection 2.2.2 1 drive connectionC141-E069-02EN 3.1 Dimensions CHAPTER 3 INSTALLATION CONDITIONS3.1 Dimensions 3.2 Mounting 3.3 Cable Connections 3.4 Jumper Settings Figure 3.1 Dimensions C141-E069-02EN3.2 Mounting Figure 3.2 OrientationFigure 3.3 Limitation of side-mounting Figure 3.4 Mounting frame structureFigure 3.5 Surface temperature measurement points Table 3.1 Surface temperature measurement points and standard valuesFigure 3.6 Service area ∙ Power supply connector CN1 ∙ ATA interface connector CN1 3.3 Cable Connections 3.3.1 Device connectorFigure 3.7 Connector locations Power supply connector CN1 Mode Setting Pins ATA interface connector3.3.3 Device connection 3.3.2 Cable connector specificationsCable connector specifications Figure 3.8 Cable connections3.3.5 System configuration for Ultra DMA 3.3.4 Power supply connector CN1Figure 3.9 Power supply connector pins CN1 Cable configuration Figure 3.11 Cable type detection using CBLID- signal Host sensing the condition of the CBLID- signal DC Power Connector 3.4 Jumper Settings 3.4.1 Location of setting jumpersFigure 3.13 Jumper location Interface ConnectorFigure 3.15 Jumper setting of master or slave device 3.4.2 Factory default settingFigure 3.14 Factory default setting 3.4.3 Jumper configuration Figure 3.18 Example 2 of Cable Select Figure 3.16 Jumper setting of Cable SelectFigure 3.17 Example 1 of Cable Select Slave Device 3 Special jumper settings a 2.1 GB clip Limit capacity to 2.1 GBMaster Device Cable SelectThis page is intentionally left blank CHAPTER 4 THEORY OF DEVICE OPERATION 4.1 Outline 4.2 Subassemblies 4.3 Circuit Configuration4.4 Power-on sequence 4.5 Self-calibration 4.6 Read/write Circuit 4.7 Servo Control4.2.2 Head C141-E069-02ENMPD3064AT Model Figure 4.1 Head structureMPD3043AT Model MPD3108AT Model4.2.5 Air filter 4.2.3 Spindle4.2.4 Actuator 4.3 Circuit Configuration Figure 4.2 MPD3xxxAT Block diagram C141-E069-02EN4.4 Power-on Sequence Figure 4.3 Power-on operation sequence 4.5.1 Self-calibration contents 4.5 Self-calibrationTable 4.1 Self-calibration execution timechart 4.5.3 Command processing during self-calibration4.6.2 Write circuit 4.6 Read/write Circuit4.6.1 Read/write preamplifier PreAMP Figure 4.4 Read/write circuit block diagram C141-E069-02EN4.6.3 Read circuit 4.7 Servo Control 4.6.4 Time base generator circuitTable 4.2 Write clock frequency and transfer rate of each zone Figure 4.5 Block diagram of servo control circuit 4.7.1 Servo control circuitFigure 4.6 Physical sector servo configuration on disk surface Servo frame 96 servo frames per revolution3 A/D converter ADC 5 Power amplifier2 Servo burst capture circuit 4 D/A converter DAC4.7.2 Data-surface servo format 4.7.3 Servo frame formatFigure 4.7 Servo frame format 4.7.4 Actuator motor control 4.7.5 Spindle motor control C141-E069-02EN 2 Acceleration mode3 Stable rotation mode CHAPTER 5 INTERFACE 5.1 Physical Interface 5.2 Logical Interface 5.3 Host Commands5.4 Command Protocol 5.5 Ultra DMA feature set 5.6 Timing Table 5.1 shows the interface signals 5.1 Physical Interface 5.1.1 Interface signalsTable 5.1 Interface signals C141-E069-02EN5.1.2 Signal assignment on the connector Table 5.2 Signal assignment on the interface connectorsignal device is ready to receive Ultra DMA data out bursts. The device may 5.2 Logical Interface 5.2.1 I/O registersTable 5.3 I/O registers 5.2.2 Command block registers 3 Features register X1F1 Diagnostic code X01 No Error Detected X02 HDC Register Compare ErrorX03 Data Buffer Compare Error X05 ROM Sum Check Error X80 Device 1 slave device FailedBit 3 HS3 CHS mode head address 3 23. LBA bit The contents of this register indicate the device and the head numberBit 7 Unused Bit 6 L. 0 for CHS mode and 1 for LBA mode Bit 5 Unused Bit 2 HS2 CHS mode head address 3 22. LBA bitC141-E069-02EN 9 Status register X1F7DRDY Always 10 Command register X1F7Always C141-E069-02EN5.3 Host Commands 5.2.3 Control block registers5.3.1 Command code and parameters Table 5.4 Command code and parameters 1 ofTable 5.4 Command code and parameters 2 of 5.3.2 Command descriptions 1F7 HCM At command issuance I/O registers setting contents1 READ SECTORS X20 or 1F6 HDH1F7 HST At command completion I/O registers contents to be readError information Status informationFigure 5.1 Execution example of READ MULTIPLE command 1 Multiword DMA transfer mode ∙ The data transfer starts at the timing of DMARQ signal assertionIn LBA mode 2 Ultra DMA transfer modeAt command issuance I/O registers setting contents At command completion I/O registers contents to be readError information 1F7 HSTAt command issuance I/O registers setting contents At command completion I/O registers contents to be readError information 1F7 HST1F7 HST At command completion I/O registers contents to be readError information Status informationError information At command issuance I/O registers setting contentsAt command completion I/O registers contents to be read ∙ The data transfer starts at the timing of DMARQ signal assertionAt command issuance I/O registers setting contents 1 Multiword DMA transfer mode2 Ultra DMA transfer mode R = 0 or At command completion I/O registers contents to be readThis command can be issued in the LBA mode At command completion I/O registers contents to be readError information At command issuance I/O registers setting contentsError information At command issuance I/O registers setting contentsAt command completion I/O registers contents to be read 10 SEEK X7x, x X0 to XFAt command completion I/O registers contents to be read In LBA modeAt command issuance I/O registers setting contents Error InformationError information At command issuance I/O registers setting contentsAt command completion I/O registers contents to be read 1F7HCMTable 5.5 Information to be read by IDENTIFY DEVICE command 1 of C141-E069-02ENTable 5.5 Information to be read by IDENTIFY DEVICE command 2 of Table 5.5 Information to be read by IDENTIFY DEVICE command 3 of Table 5.5 Information to be read by IDENTIFY DEVICE command 4 of Error information At command issuance I/O registers setting contentsAt command completion I/O registers contents to be read 14 SET FEATURES XEFTable 5.6 Features register values and settable modes At command completion I/O registers contents to be read At command issuance I/O registers setting contentsxx or transfer mode Error informationAt command completion I/O registers contents to be read 15 SET MULTIPLE MODE XC6At command issuance I/O registers setting contents Error information16 EXECUTE DEVICE DIAGNOSTIC Word 59 = 0000 The READ MULTIPLE and WRITE MULTIPLE commands aredisabled = When device 1 is not presentTable 5.7 Diagnostic code R = 0 or At command completion I/O registers contents to be read The READ LONG command supports only single sector operationAt command issuance I/O registers setting contents Error informationError information At command issuance I/O registers setting contentsR = 0 or At command completion I/O registers contents to be read At command issuance I/O registers setting contentsAt command issuance I/O registers setting contents At command completion I/O registers contents to be readError information At command completion I/O registers contents to be readAt command issuance I/O registers setting contents Point of timerDisable of timer Period of timerAt command issuance I/O registers setting contents At command completion I/O registers contents to be readError information At command completion I/O registers contents to be readAt command completion I/O registers contents to be read At command issuance I/O registers setting contentsPeriod of timer Error informationError information At command issuance I/O registers setting contentsAt command completion I/O registers contents to be read This command is the only way to make the device enter the sleep mode27 CHECK POWER MODE X98 or XE5 At command completion I/O registers contents to be readError information The host checks the power mode of the device with this commandError information At command issuance I/O registers setting contentsAt command completion I/O registers contents to be read 1F7 HCMTable 5.8 Features Register values subcommands and functions At command completion I-O registers setting contents At command issuance I-O registers setting contentsSubcommand Error informationTable 5.9 Format of device attribute value data Table 5.10 Format of insurance failure threshold value data Power-on time Read error rateSeek error rate Number of power-on-power-off timesBits 2 to 15 Reserved bits ∙ Check sum ∙ Raw attribute value Raw attributes data is retained∙ Failure prediction capability flag ∙ Insurance failure thresholdAt command completion I/O registers contents to be read NOTE - This command may take longer than 30 s to completeAt command issuance I/O registers setting contents Error informationTable 5.11 Contents of security password Error information At command issuance I-O registers setting contentsAt command completion I-O registers setting contents 1F7 HCMError information At command issuance I-O registers setting contentsAt command completion I-O registers setting contents 1F7 HCMError information At command issuance I-O registers setting contentsAt command completion I-O registers setting contents ∙ SECURITY SET PASSWORD ∙ SECURITY UNLOCK ∙ SECURITY DISABLE PASSWORDAt command issuance I-O registers setting contents SECURITY DISABLE PASSWORDSECURITY SET PASSWORD At command completion I-O registers setting contentsbetween combination of Identifier and Security level, and Table 5.12 Contents of SECURITY SET PASSWORD dataTable 5.13 Relationship operation of the lock functionError information At command issuance I-O registers setting contentsAt command completion I-O registers setting contents 35 SECURITY UNLOCK F2h This command cancels LOCKED MODEError information At command issuance I-O registers setting contentsAt command completion I-O registers setting contents 1F7 HCMError information At command issuance I/O registers setting contentsAt command completion I/O registers contents to be read At command issuance I/O registers setting contents1F7HST At command completion I/O registers contents to be readError information Status informationDRDY 5.3.3 Error postingTable 5.14 Command code and parameters 5.4 Command Protocol 5.4.1 Data transferring commands from device to hostFigure 5.2 Read Sectors command protocol Figure 5.3 Protocol for command abort 5.4.2 Data transferring commands from host to deviceFigure 5.4 WRITE SECTORS command protocol 5.4.3 Commands without data transfer Figure 5.5 Protocol for the command execution without data transfer5.4.4 Other commands 5.4.5 DMA data transfer commandsFigure 5.6 Normal DMA data transfer 5.5 Ultra DMA feature set 5.5.1 Overview 5.5.3.1 Initiating an Ultra DMA data in burst 5.5.2 Phases of operation5.5.3 Ultra DMA data in commands 5.5.3.3 Pausing an Ultra DMA data in burst 5.5.3.2 The data in transfer5.5.3.4 Terminating an Ultra DMA data in burst b Host terminating an Ultra DMA data in burst C141-E069-02EN5.5.4 Ultra DMA data out commands 5.5.4.1 Initiating an Ultra DMA data out burst5.5.4.3 Pausing an Ultra DMA data out burst 5.5.4.2 The data out transfer5.5.4.4 Terminating an Ultra DMA data out burst b Device terminating an Ultra DMA data out burst C141-E069-02EN5.5.5 Ultra DMA CRC rules Figure 5.7 Ultra DMA termination with pull-up or pull-down 5.5.6 Series termination required for Ultra DMATable 5.15 Recommended series termination for Ultra DMA 5.6 Timing 5.6.1 PIO data transfer Figure 5.8 PIO data transfer timingFigure 5.9 Multiword DMA data transfer timing mode 5.6.2 Multiword data transferFigure 5.10 Initiating an Ultra DMA data in burst 5.6.3 Ultra DMA data transfer5.6.3.1 Initiating an Ultra DMA data in burst 5.6.3.2 Ultra DMA data burst timing requirements Table 5.16 Ultra DMA data burst timing requirements 1 oftACK Table 5.16 Ultra DMA data burst timing requirements 2 oftZIORDY UIMLI5.6.3.3 Sustained Ultra DMA data in burst Figure 5.11 Sustained Ultra DMA data in burst5.6.3.4 Host pausing an Ultra DMA data in burst Figure 5.12 Host pausing an Ultra DMA data in burst5.6.3.5 Device terminating an Ultra DMA data in burst Figure 5.13 Device terminating an Ultra DMA data in burst5.6.3.6 Host terminating an Ultra DMA data in burst Figure 5.14 Host terminating an Ultra DMA data in burst5.6.3.7 Initiating an Ultra DMA data out burst Figure 5.15 Initiating an Ultra DMA data out burst5.6.3.8 Sustained Ultra DMA data out burst Figure 5.16 Sustained Ultra DMA data out burst5.6.3.9 Device pausing an Ultra DMA data out burst Figure 5.17 Device pausing an Ultra DMA data out burst5.6.3.10 Host terminating an Ultra DMA data out burst Figure 5.18 Host terminating an Ultra DMA data out burst5.6.3.11 Device terminating an Ultra DMA data in burst Figure 5.19 Device terminating an Ultra DMA data out burst5.6.4 Power-on and reset Figure 5.20 Power-on Reset TimingThis page is intentionally left blank 6.6 Write Cache 6.1 Device Response to the Reset 6.1 Device Response to the Reset 6.2 Address Translation6.3 Power Save 6.4 Defect Management 6.5 Read-Ahead Cache CHAPTER 6 OPERATIONS6.1.1 Response to power-on Figure 6.1 Response to power-on6.1.2 Response to hardware reset Figure 6.2 Response to hardware reset6.1.3 Response to software reset Figure 6.3 Response to software reset6.1.4 Response to diagnostic command Figure 6.4 Response to diagnostic command6.2 Address Translation 6.2.1 Default parametersTable 6.1 Default parameters MPD3043ATFigure 6.5 Address translation example in CHS mode 6.2.2 Logical addressFigure 6.6 Address translation example in LBA mode 6.3 Power Save 6.3.1 Power save mode∙ Power-on sequence is completed 1 Active modeA device enters the active mode under the following conditions ∙ A command other than power commands is issued6.3.2 Power commands 6.4 Defect ManagementFigure 6.7 Sector slip processing 6.4.1 Spare area6.4.2 Alternating defective sectors DefectiveFigure 6.8 Alternate cylinder assignment unused6.5 Read-Ahead Cache 6.5.1 Data buffer configurationFigure 6.9 Data buffer configuration 6.5.2 Caching operation 6.5.3 Usage of read segment Mis-hit data a. Sequential command just after non-sequential command3 Sequential read Empty dataRead-ahead data b. Sequential hitHAP Completion of transferring requested data Hit data3 Full hit hit all Last position at previous read commandDAP Last position at previous read command HAP set to hit position for data transferstopped 6.6 Write Cache When the write cache function is enabled, the transferred data from the host by the WRITE SECTORS is not completely written on the disk medium at the time that the interrupt of command complete is generated. When the unrecoverable error occurs during the write operation, the command execution is stopped. Then, when the drive receives the next command, it generates an interrupt of abnormal end. However an interrupt of abnormal end is not generated when a write automatic assignment succeeds. However, since the host may issue several write commands before the drive generates an interrupt of abnormal end, the host cannot recognize that the occurred error is for which command generally. Therefore, it is very hard to retry the unrecoverable write error for the host in the write cache operation generally. So, take care to use the write cache function I, Place des Etas-Unis, SILIC 310, 94588 Rungis Cedex, FRANCE FUJITSU LIMITED Reader Comment Form