Model 5328A

 

 

Schematic Diagrams

 

Table 8-1. Signal Mnemonics (Continued)

 

 

 

 

MNEMONIC

 

DESCRIPTION

 

 

 

 

 

RL (HTBB)

 

Latched ROM bit which enables the TTL level Channel B

 

 

 

signal from the Function Selector to be counted by the

 

 

 

Time Base.

 

R (HTBO)

 

Non-latched ROM bit which enables the time base to count

 

 

 

the oscillator output.

 

RL (IA)

 

TTL level latched ROM bits that drive High Speed

 

RL (IB)

 

Multiplexer select lines on Function Selector.

 

RL (IC)

 

 

 

L ANN

 

Low annunciators. TTL active low turns RHS annunciators

 

 

 

on. Must be timed with digit address code to display

 

 

 

selected annunciators.

 

LDDCA

 

Low disable Decade Counting Assembly (DCA). TTL active

 

 

 

low disables DCA so that all DCA outputs are high.

 

LDI

 

Low disable indicators. TTL active low blanks RHS

 

 

 

annunciators and all decimal points.

 

LDDIS

 

Low disable display. TTL active low blanks display except

 

 

 

LHS annunciators.

 

LDP

 

Low decimal point. TTL active low turns decimal points on.

 

 

 

Must be timed with digit address code to display selected

 

 

 

decimal points.

 

LDSW

 

Low disable switches. The active low disables the FUNCTION

 

 

 

RESOLUTION and RESET switches. Allows module control.

 

LEXT

 

Low external. TTL active low disables function and

 

 

 

resolution switches for external control and lights RM

 

 

 

annunciator.

 

LINH

 

Low inhibit. TTL active low inhibits starting new

 

 

 

measurement.

 

LMG

 

Low main gate. TTL active low indicates main gate open.

 

RL (LMGF)

 

Latched ROM bit to Function Selector which selects the main

 

 

 

gate F/F on the Function Selector to establish the gate time.

 

LMRES

 

Low when reset signal comes from display. Provides power-

 

 

 

up type reset.

 

LRES

 

Low reset. TTL active low resets when FUNCTION,

 

 

 

RESOLUTION, or RESET switch settings are changed.

 

 

 

Also resets when DVM switches are changed. Provides

 

 

 

power-up type of reset.

 

R (LST)

 

Non-latched ROM line which is high in stop totalize and low

 

 

 

in start.

 

RL (LTOT)

 

Low totalize. Latched ROM bit low in totalize mode.

 

 

 

TTL level.

 

LTR

 

Low transfer. TTL active low used in DCA.

 

MG

 

Main gate. Accurate signal to drive remote gate such as

 

M G

 

channel C. ECL levels.

 

OSC

 

10 MHz oscillator. TTL level.

 

 

 

 

 

8-5

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Image 160
HP E42 manual Htbo, Rl Ia, Rl Ic Ann, Lddca, Lmg, RL Ltot