HP E42 manual An Example of Operation, 103.A16 Display Assembly

Model 5328A

Theory of Operation

4-96.Time Base Multiplexer and Main Gate FF

4-97.Time Base Multiplexer U10 select either A, B, or OSC to send the Time Base Input (TBI) signal via pin 8 to the Time Base. This same signal is also sent to U1, the Main Gate FF, as a desynchronizing signal. ROM lines R(HTBA), R(HTBO), and R(HTBB) control the selection of the Time Base Input signal. The HDS signal to U10(3) or ROM line LTOT to U10(1) serve to enable or disable U10.

4-98.U1B is a high-speed ECL FF used to generate precise stable gate times for the Main Gate Multiplexer U8 and the remote gate in the Frequency C module. A TTL replica of the Main Gate signal (GATE OUT) is generated in the Time Base and sent to U1 via the line Main Gate Synchronizer on the Motherboard. Resistors R14 and R43B translate this TTL signal down to ECL levels at U1(10). The output of Time Base Multiplexer U10 via resistors R42 and R43D and capacitor C16 clocks U1(11) yielding a synchronized fast rise and fall time Main Gate signal on U1(14).

4-99.An Example of Operation

4-100.To show how the above mentioned function selector circuits operate together an ex- ample of the measurement of frequency A is given in the following paragraphs.

4-101.Assume the counter is in the middle of its display cycle. Low Inhibit (LINH) is TTL low, High Reset Time Base (HRTB) has momentarily gone high resetting U1 and U4 and High Reset Decade (HRD) has momentarily gone high resetting First Decade U1, U4, and U4. The control chip on the Motherboard releases LINH to go high. U9(13) goes low enabling Arming Multiplexer US. Assuming that self arm has been selected, A will have been dected by the ROM , on pins 9, 10, and 11 of U5. When the first A pulse occurs U4(4) goes low setting U4. U4(5) goes high turning on transistor Q1 which in turn pulls LINH low again and inhibits another measure- ment from starting until Reset has occurred. In a frequency measurement, the ROM selects the Oscillator signal on pin 2 of U10 to be sent into the Time Base. Shortly after the Time Base re- turns, a high signal on Main Gate Synchronizer drives U1(10) high. On the next Oscillator signal (through U10) U10(11) gets clocked causing U1(14) to go low. This low signal propagates through U8(B and C) to U62) opening the Main Gate and initiating the count, Signal A has been selected on U6 by ROM lines R22, 23, and 24 thus each A event is counted into 1st decade U1A, U4A, and U3.

4-102.After the appropriate gate time has elapsed (N clock counts into the Time Base) the Main Gate Syncrhonizer signal goes low and the next Oscillator signal clocks Main Gate FF U1 closed. U2(10) detects the closing of the Main Gate and sends a TTL signal (LMGF) to U4 in the State Control section of the Al Motherboard which initiates a new display cycle.

4-103.A16 DISPLAY ASSEMBLY

4-104.The Display Assembly contains the display, as shown in the block diagram in Section Vlll, in addition to switches S1 (POWER), S2 (RESET), S3 (FUNCTION), S4 (FREQ RESO- LUTION, N) and SAMPLE RATE control R6 as shown in the schematic diagram in Section Vlll.

4-105.The display consists of a nine-digit seven-segment LED numeric display (DS1-DS9) and annunciators for indicating measurement units (DS10-DSI6) in addition to overflow (DS17), remote (DS18), and gate (DS19). The display digits and annunciators are automatically dis- played with the correct decimal point.

4-106.The digit address code from A1U39 on the Motherboard is applied to transistors Q1 through Q9 to strobe each digit which receives the seven-segment code from A1U41 through transistors Q13-Q20. The gate (DS19), remote (DS18), and overflow (DS17) LED’s receive signals from the Motherboard through transistors Q10, Q11, and Q12, respectively.

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