Program Structure
Registers and Register Mnemonics
Registers and Register Mnemonics
PA-RISC processors have four sets of registers:
•General
•Floating-point
•Space
•Control
Data is loaded from memory into general or floating-point registers and stored into memory from general or floating-point registers. Arithmetic and logical operations are performed on the contents of the general registers. On PA-RISC 1.0 or 1.1 each general register is 32 bits wide. On PA-RISC 2.0 each general register is 64 bits wide. On PA-RISC 2.0W (true 64-bit environment) each general register is 64 bits wide.
There are 32 general registers, denoted as %r0 through %r31. General register %r0 is special because “writes” into it are ignored, and it always reads as zero. The remaining general registers can be used normally, with the caution that %r1 is the implicit target register for the ADDIL instruction, %r31 is the implicit link register for the BLE instruction, and for PA-RISC 2.0 only, %r2 is the implicit link register for the BLVE instruction. Certain general registers also have predefined conventional uses. Refer to “Register Procedure Calling Conventions” on page 28. You can find detailed information on both 32-bit and 64-bit runtime architecture under the topic PA-RISC Architecture at http://www.software.hp.com/STK/.
PA-RISC 1.0 machines have 16 floating-point registers; PA-RISC 1.1, 2.0, and 2.0W (true 64-bit environment) machines have 32 floating-point registers. Each register is capable of holding either a single- or double-precision floating-point number in IEEE format. These registers are denoted %fr0 through %fr15 for PA-RISC 1.0 and %fr0 through %fr31 for PA-RISC 1.1, 2.0, and 2.0W.
Registers %fr1, %fr2, and %fr3 are exception registers and are not available to the programmer. Floating-point register %fr0 contains a permanent floating-point zero when used in an arithmetic operation; when written or read with floating-point loads or stores, the floating-point status register is actually accessed.