EM78P809N

8-Bit Microcontroller

ISFR2 Interrupt Status Flag Register 2 ( Address: 0Fh )

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0

UERRIF

RBFF

TBEF

TBIF

EXIF1

0

TCIF0

Bit 6 (UERRIF) : UART Receiving Error Interrupt, cleared by software or UART disabled.

Bit 5 (RBFF) : UART Receive Mode Data Buffer Full Interrupt Flag. Flag cleared by software.

Bit 4 (TBEF) : UART Transmit Mode Data Buffer Empty Interrupt Flag. Flag cleared by software.

Bit 3 (TBIF) : Time Base Timer Interrupt Flag. Flag cleared by software.

Bit 2 (EXIF1) : External Interrupt Flag (INT1). Flag cleared by software.

Bit 0 (TCIF0) : TCC Overflow Interrupt Flag. Set as TCC overflows; flag cleared by software.

"1" means interrupt request, "0" means non-interrupt

—ISFR2 can be cleared by instruction, but cannot be set by instruction

—IMR2 is the interrupt mask register

—Note that reading ISFR2 will obtain the result of the ISFR2 "logic AND" and IMR2

Register Bank 1 ( R3 bits ( 7,6) = (0,1) )

TC3CR Timer/Counter 3 Control Register ( Address: 05h )

Bit 7

 

Bit 6

 

Bit 5

 

Bit 4

Bit 3

 

Bit

2

 

Bit

1

 

Bit

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TC3CAP

TC3S

TC3CK1

TC3CK0

TC3M

 

0

 

 

0

 

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bit 7 ( TC3CAP ) : Software capture control

TC3CAP = “0” : -

TC3CAP = “1” : Software capture

Bit 6 ( TC3S ) : Timer/Counter 3 start control

TC3S = “0” : Stop and counter clear

TC3S = “1” : Start

Product Specification (V1.0) 07.26.2005

13

(This specification is subject to change without further notice)

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IBM EM78P809N manual Bit 7 TC3CAP Software capture control, TC3CAP =, TC3S = 1 Start, TC3CAP TC3S TC3CK1 TC3CK0 TC3M