ADC Data Register, Sampling Time, Conversion Time | IBM EM78P809N

EM78P809N

8-Bit Microcontroller

AD7 (P97)
AD7 (P97)
AD6 (P96)								8


AD5 (P95)

									to 1

AD4 (P94)

									Analog


AD3 (P93)									switch
AD3 (P93)
AD2 (P92)



AD1 (P91)
AD1 (P91)
AD0 (P90)





	7 - 0					2			1

Fosc/4

Fosc/16 4 to 1 Fosc/32 MUX


0		5	4

ADC

(Successive Approximation)


5		5			9	8	7	6	5	4	3	2	1	0

VDD

VREF

Power Down

Start to Convert

6		3		7

ADIC	ADCR

ADCR	ISFR1		IMR1

ADCR

DATA BUS

Fig. 6. AD Converter

It is a 10-bit successive approximation type AD converter. The upper side of analog reference voltage can select either internal VDD or external input pin P97 (VREF) by setting the ADREF bit in ADCR.

ADC Data Register:

When the A/D conversion is complete, the result is loaded to the ADDH (8 bit) and ADDL (2 bit). The START/END bit is cleared, and the ADIF is set.

A/D Sampling Time:

The accuracy, linearity, and speed of the successive approximation A/D converter are dependent on the properties of the ADC. The source impedance and the internal sampling impedance directly affect the time required to charge the sample holding capacitor. The application program controls the length of the sample time to meet the specified accuracy. Generally speaking, the program should wait for 2 μs for each KΩ of the analog source impedance and at least 2 μs for the low-impedance source. The maximum recommended impedance for the analog source is 10KΩ at VDD =5V. After the analog input channel is selected, this acquisition time must be done before A/D conversion can be started.

A/D Conversion Time:

ADCK0 and ADCK1 select the conversion time (Tct), in terms of instruction cycles. This allows the MCU to run at maximum frequency without sacrificing accuracy of A/D conversion. For the EM78P809N, the conversion time per bit is about 4μs. Table 5 shows the relationship between Tct and the maximum operating frequencies.

30 •	Product Specification (V1.0) 07.26.2005

(This specification is subject to change without further notice)

Image 34

IBM EM78P809N manual ADC Data Register, Sampling Time, Conversion Time

Contents

EM78P809N DOC. Version Elan Microelectronics Corporation Contents Specification Revision History CPU Bit Microcontroller Applications „ General purpose Pin Assignment OTP Programming Pins Functional Block Diagram Function Description Operating Registers Tbktc R1/TCC − Time Clock /Counter Address 01h R2/PC − Program Counter & Stack Address 02h Bit 5 Not used R3/SR − Status Register Address 03hBit 7 ~ Bit 6 RBS1 ~ RBS0 R-Register page select RBS1 RBS0 GRBS1 GRBS0 Bit 0 C Carry flag R4/RSR − RAM Select Register Address 04hGeneral Purpose Register Bank Address 20H ~ 3FH PORT7 Port 7 I/O Data Register Address 07h SIS = 0 Idle mode SIS = 1 Sleep modePORT6 − Port 6 I/O Data Register Address 06h PORT8 − Port 8 I/O Data Register Address 08h TC4FF1 TC4FF0 TC4CR Timer/Counter 4 Control Register Address 0BhTC4S = 1 Start TC4CK2 TC4CK1 TC4CK0 Bit Microcontroller TC4D − Timer 4 Data Buffer Address 0Ch ISFR1 − Interrupt Status Flag Register 1 Address 0Eh TC3S = 1 Start Bit 7 TC3CAP Software capture controlTC3CAP = TC3CAP TC3S TC3CK1 TC3CK0 TC3M Bit 7 ~ Bit 6 ADD1 ~ ADD0 AD low 2-bit data buffer TC3DB − Timer 3 Data Buffer B Address 07hTC2M = 1 Window mode TC2S = 1 Start TC2DL − Timer 2 Data Buffer Low Byte Address 0Ah TC2DH − Timer 2 Data Buffer High Byte Address 09hAdcr − AD Control Register Address 0Bh Adic − AD Input Pin Control Address 0Ch Bit 3 ADP AD power controlBit 7 ~ Bit 0 ADE7 ~ ADE0 AD input pin enable control Addh − AD High 8-bit Data Buffer Address 0Dh Bit 3 Tbten Time Base Timer Enable Control Bit 7 TEN Keytone enable controlTEN = 0 Disable TEN = 1 Enable Bit Microcontroller Tbktc − TBT/Keytone Control Address 0Eh Uinven = 1 Enable TXD and RXD port inverse output Bit 3 Uinven Enable Uart TXD and RXD port inverse outputUinven = 0 Disable TXD and RXD port inverse output Bit 4 ~ Bit 2 BRATE2 ~ BRATE1 Transmit Baud Rate Select Bit Microcontroller URS − Uart Status Register Address 07h Bit 5 PRE Enable parity additionEven = 0 Odd parity Even = 1 Even parity SMP Dcol BRS2 BRS1 Bit 2 EDS Data shift out edge selectEDS = 0 Rising edge EDS = 1 Falling edge EDS Dord WBE Spid SPI Data Buffer Address 07h Transfer ModeSPIC2 − SPI Control Register 2 Address 06h SPID7 SPID6 SPID5 SPID4 SPID3 SPID2 SPID1 SPID0 PHC2 − Pull High Control Register 2 Address 0Ch PLE7x = 1 Disable P7x pull lowPLC1 Pull Low Control Register 1 Address 0Bh PLC2 − Pull Low Control 2 Address 0Dh Control Register Special Purpose RegistersAccumulator Bit 7 Wdto WDT output select Bit 2 Reserved Bit Microcontroller IOC6 ~ IOC9 − I/O Port Control RegisterIntcr − INT Control Register Address 0Bh INT1ES = 0 Rising edge INT1ES = 1 Falling edge Adoscr − AD Offset Control Register Address 0Ch INT Pin Secondary Enable Condition Function PinExternal Interrupt Edge IMR2 − Interrupt Mask Register 2 Address 0Fh Uerrie Urie Utie Tbie EXIE1 TCIE0 Rbank Register Bank bits 7, 6 of R3, R/W Read/Write CPU Operation ModeRegisters for CPU operation mode Rbank Operation Mode Mode Switching ControlNormal → Don’t care → Interrupt request flag will be recorded AD ConverterRegisters for AD Converter Circuit Sampling Time ADC Data RegisterConversion Time ADCK10 Time Base Timer and Keytone GeneratorMax. Frequency Max. Conversion Rate per Bit Tone Output Pin Timing Chart Registers for Uart Circuit Uart Universal Asynchronous Receiver/TransmitterRbank Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit Uart Mode Data Format in Uart Transmitting Receiving Baud Rate Generator SPI Serial Peripheral InterfaceRegisters for the SPI Circuit Bit Transmit Mode Shift Direction and Sample PhaseTransfer Mode Serial Clock Bit Microcontroller Bit Receive Mode Bit Transmit/Receive Mode SCK pin Multiple Device Connect /SS Registers for Timer/Counter 2 Circuit Timer/CounterRbank Address Name Bit 7 Bit 6 Bit Counter Mode Timer ModeWindow Mode Window Mode Timing Chart Registers for Timer/Counter 3 Circuit Capture mode Configuration of Timer/Counter3 Registers for Timer 4 Circuit TCIF4 PDO Mode TCR4 12 TCC/WDT & Prescaler PWM ModeTC4 Interrupt Reset Reset and Wake-up13 I/O Ports Wake-up from Idle mode Wake-up from Sleep ModeAll interrupt Address Name Reset Type Bit Summary of the Initialized Values for Registers Bit Microcontroller Register Bank SCR TC2D9 TC2D8 Register Bank Status of RST, T, and P of Status Register Previous value before resetReset Type Bit Microcontroller General Purpose Registers Controller Reset Block Diagram Interrupt Crystal Oscillator/Ceramic Resonators Crystal OscillatorOscillator Modes Summary of Maximum Operating Speeds Ext. Clock Oscillator Type Frequency Mode C1 pF C2 pFEM78P809N 740 External RC Oscillator Mode Crystal/Resonator-Parallel Mode Circuit Code Option Register Word Enwdtb = 0 Enable Enwdtb = 1 DisableCode Option Register For design reference only Customer ID Register Power-on ConsiderationsExternal Power-on Reset Circuit Cyes = 0 One cycle Cyes = 1 Two cycles EM78P809N Rin Residue-Voltage ProtectionVdd Vdd EM78P809N Instruction Set Vdd 40KR2 Binary Instruction Hex Mnemonic Operation Status Affected DEC Recommended Operating Conditions Symbol Parameter Condition Min Typ Max UnitAbsolute Maximum Ratings Vss = Ta= 25 C, VDD= 5.0V ± 5%, VSS= DC Electrical CharacteristicsTypical value is based on characterization results at 25C Ta= 25 C, VDD= 3.0V ± 5%, VSS= Varef Ta=- 40C ~ 85 C, VDD=5V ± 5%, VSS=0V AC Electrical CharacteristicSymbol Parameter Conditions Min Typ Max Unit = selected prescaler ratio Timing Diagram AC Test Input/Output Waveform OTP MCU Package TypesPin Count Package Size Contents III EM78P809N