IBM EM78P809N manual External Interrupt, Adoscr − AD Offset Control Register Address 0Ch, Edge

Models: EM78P809N

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EM78P809N

8-Bit Microcontroller

External Interrupt

INT Pin

Secondary

 

Enable Condition

 

Function Pin

 

 

 

 

 

 

 

 

 

 

 

/INT0

P60

 

ENI + INT0EN (IOCB)

 

 

 

 

 

 

INT1

P61

 

ENI + EXIE1 (IMR2)

 

 

 

 

 

 

INT3

P80, TC3

 

ENI + EXIE3 (IMR2)

 

 

 

 

 

 

/INT5

P73, /SLEEP

 

ENI + EXIE5 (IMR2)

 

 

 

 

 

 

Edge

Falling

Rising or Falling

Rising or Falling or

Rising/Falling

Digital Noise

Reject

-

15/Fc, 63/Fc

7/Fc

-

ADOSCR AD Offset Control Register ( Address : 0Ch )

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

 

 

 

 

 

 

Bit 1

Bit 0

CALI

SIGN

VOF[2]

VOF[1]

VOF[0]

0

0

0

Bit 7 (CALI) : Calibration enable bit for A/D offset CALI = “0” : Calibration disable

CALI = “1” : Calibration enable Bit 6 ( SIGN ) : Polarity bit of offset voltage

SIGN = “0” : Negative voltage

SIGN = “1” : Positive voltage

Bit 5 ~ Bit 3 ( VOF[2] ~ VOF[0] ) : Offset voltage bits

IMR1 Interrupt Mask Register 1 ( Address : 0Eh )

Bit 7

Bit 6

Bit 5

Bit 4

 

 

 

 

Bit 3

Bit 2

Bit 1

Bit 0

 

 

 

EXIE5

TCIE2

ADIE

0

EXIE3

TCIE4

SPIE

TCIE3

Bit 7 ( EXIE5 ) : External/INT5 pin Interrupt enable bit.

EXIE5 = “0” : disable EXIF5 interrupt

EXIE5 = “1” : enable EXIF5 interrupt

Bit 6 ( TCIE2 ) : Timer/Counter 2 Interrupt enable bit.

TCIE2 = “0” : disable TCIF2 interrupt

TCIE2 = “1” : enable TCIF2 interrupt

Bit 5 ( ADIE ) : ADC complete interrupt enable bit.

ADIE = “0” : disable ADIF interrupt

ADIE = “1” : enable ADIF interrupt

Product Specification (V1.0) 07.26.2005

25

(This specification is subject to change without further notice)

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IBM EM78P809N manual External Interrupt, Adoscr − AD Offset Control Register Address 0Ch, Edge, Digital Noise Reject