GRBS1 GRBS0 | IBM EM78P809N specs

EM78P809N

8-Bit Microcontroller

Bit 3 (P) : Power down bit. Set to “1” during power on or by a "WDTC" command and reset to “0” by a "SLEP" command.

Bit 2 (Z) : Zero flag. Set to "1" if the result of an arithmetic or logic operation is zero.

Bit 1 (DC) : Auxiliary carry flag

Bit 0 (C) : Carry flag

R4/RSR − RAM Select Register ( Address: 04h )

Bit 7	Bit 6	Bit 5	Bit 4

Bit 3

Bit 2	Bit 1	Bit 0

GRBS1

RBS0

RSR5

RSR4

RSR3

RSR2

RSR1

RSR0

Bit 7: 6 ( GRBS1 : GRBS0 ) : determine which general purpose banks are activated among the 4 banks. Use BANK instruction (e.g. BABK 1) to change bank.

GRBS1		GRBS0		General Purpose Register Bank (Address 20H ~ 3FH)

0		0		Bank 0

0		1		Bank 1

1		0		Bank 2

1		1		Bank 3

Bit 5: 0 ( RSR5 : RSR0 ) : are used to select the registers (address: 00h~3Fh) in the indirect addressing mode. If no indirect addressing is used, the RSR can be used as an 8-bit general-purpose read/write register. See the data memory configuration in Fig. 3.

Register Bank 0 ( R3 bits (7, 6) = (0, 0) )

SCR − System Control Register, Program ROM Page Select ( Address: 05h )

	Bit 7	Bit 6	Bit 5	Bit 4

Bit 3

	Bit 2	Bit 1	Bit 0

0

PS2

PS1

PS0

0

1

SIS

REM

Bit 6 (PS2) ~ 4 (PS0) : ROM Page select bits. User can use PAGE instruction (e.g. PAGE 1) or set PS2~PS0 bits to change the ROM page. When executing a "JMP", "CALL", or other instructions which cause the program counter to change (e.g. MOV R2, A), PS2~PS0 are loaded into the 13th to 11th bits of the program counter and select one of the available program memory pages. Note that RET (RETL, RETI) instruction does not change the PS2~PS0 bits. That is, return will always be to the page from where the subroutine was called, regardless of the PS2~PS0 bits current setting.

Product Specification (V1.0) 07.26.2005

• 9

(This specification is subject to change without further notice)

Image 13

IBM EM78P809N manual Bit 0 C Carry flag R4/RSR − RAM Select Register Address 04h, GRBS1 GRBS0

Contents

DOC. Version EM78P809N Elan Microelectronics Corporation Contents Specification Revision History Bit Microcontroller CPU „ General purpose Applications Pin Assignment OTP Programming Pins Function Description Functional Block Diagram Tbktc Operating Registers R2/PC − Program Counter & Stack Address 02h R1/TCC − Time Clock /Counter Address 01h Bit 7 ~ Bit 6 RBS1 ~ RBS0 R-Register page select R3/SR − Status Register Address 03hBit 5 Not used RBS1 RBS0 GRBS1 GRBS0 Bit 0 C Carry flag R4/RSR − RAM Select Register Address 04hGeneral Purpose Register Bank Address 20H ~ 3FH PORT6 − Port 6 I/O Data Register Address 06h SIS = 0 Idle mode SIS = 1 Sleep modePORT7 Port 7 I/O Data Register Address 07h PORT8 − Port 8 I/O Data Register Address 08h TC4S = 1 Start TC4CR Timer/Counter 4 Control Register Address 0BhTC4FF1 TC4FF0 TC4CK2 TC4CK1 TC4CK0 ISFR1 − Interrupt Status Flag Register 1 Address 0Eh Bit Microcontroller TC4D − Timer 4 Data Buffer Address 0Ch TC3CAP = Bit 7 TC3CAP Software capture controlTC3S = 1 Start TC3CAP TC3S TC3CK1 TC3CK0 TC3M TC2M = 1 Window mode TC3DB − Timer 3 Data Buffer B Address 07hBit 7 ~ Bit 6 ADD1 ~ ADD0 AD low 2-bit data buffer TC2S = 1 Start TC2DL − Timer 2 Data Buffer Low Byte Address 0Ah TC2DH − Timer 2 Data Buffer High Byte Address 09hAdcr − AD Control Register Address 0Bh Bit 7 ~ Bit 0 ADE7 ~ ADE0 AD input pin enable control Bit 3 ADP AD power controlAdic − AD Input Pin Control Address 0Ch Addh − AD High 8-bit Data Buffer Address 0Dh TEN = 0 Disable TEN = 1 Enable Bit 7 TEN Keytone enable controlBit 3 Tbten Time Base Timer Enable Control Bit Microcontroller Tbktc − TBT/Keytone Control Address 0Eh Uinven = 0 Disable TXD and RXD port inverse output Bit 3 Uinven Enable Uart TXD and RXD port inverse outputUinven = 1 Enable TXD and RXD port inverse output Bit 4 ~ Bit 2 BRATE2 ~ BRATE1 Transmit Baud Rate Select Bit Microcontroller URS − Uart Status Register Address 07h Bit 5 PRE Enable parity additionEven = 0 Odd parity Even = 1 Even parity EDS = 0 Rising edge EDS = 1 Falling edge Bit 2 EDS Data shift out edge selectSMP Dcol BRS2 BRS1 EDS Dord WBE SPIC2 − SPI Control Register 2 Address 06h Transfer ModeSpid SPI Data Buffer Address 07h SPID7 SPID6 SPID5 SPID4 SPID3 SPID2 SPID1 SPID0 PLC1 Pull Low Control Register 1 Address 0Bh PLE7x = 1 Disable P7x pull lowPHC2 − Pull High Control Register 2 Address 0Ch PLC2 − Pull Low Control 2 Address 0Dh Accumulator Special Purpose RegistersControl Register Bit 7 Wdto WDT output select Intcr − INT Control Register Address 0Bh Bit Microcontroller IOC6 ~ IOC9 − I/O Port Control RegisterBit 2 Reserved INT1ES = 0 Rising edge INT1ES = 1 Falling edge External Interrupt INT Pin Secondary Enable Condition Function PinAdoscr − AD Offset Control Register Address 0Ch Edge Uerrie Urie Utie Tbie EXIE1 TCIE0 IMR2 − Interrupt Mask Register 2 Address 0Fh Registers for CPU operation mode CPU Operation ModeRbank Register Bank bits 7, 6 of R3, R/W Read/Write Rbank Operation Mode Mode Switching ControlNormal → Don’t care → Interrupt request flag will be recorded AD ConverterRegisters for AD Converter Circuit Sampling Time ADC Data RegisterConversion Time ADCK10 Time Base Timer and Keytone GeneratorMax. Frequency Max. Conversion Rate per Bit Tone Output Pin Timing Chart Registers for Uart Circuit Uart Universal Asynchronous Receiver/TransmitterRbank Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit Data Format in Uart Uart Mode Receiving Transmitting Baud Rate Generator SPI Serial Peripheral InterfaceRegisters for the SPI Circuit Transfer Mode Shift Direction and Sample PhaseBit Transmit Mode Serial Clock Bit Transmit/Receive Mode Bit Microcontroller Bit Receive Mode Multiple Device Connect /SS SCK pin Registers for Timer/Counter 2 Circuit Timer/CounterRbank Address Name Bit 7 Bit 6 Bit Counter Mode Timer ModeWindow Mode Registers for Timer/Counter 3 Circuit Window Mode Timing Chart Configuration of Timer/Counter3 Capture mode TCIF4 Registers for Timer 4 Circuit TCR4 PDO Mode 12 TCC/WDT & Prescaler PWM ModeTC4 Interrupt Reset Reset and Wake-up13 I/O Ports Wake-up from Idle mode Wake-up from Sleep ModeAll interrupt Summary of the Initialized Values for Registers Address Name Reset Type Bit SCR Bit Microcontroller Register Bank TC2D9 TC2D8 Register Bank Reset Type Previous value before resetStatus of RST, T, and P of Status Register Bit Microcontroller General Purpose Registers Interrupt Controller Reset Block Diagram Oscillator Modes OscillatorCrystal Oscillator/Ceramic Resonators Crystal Summary of Maximum Operating Speeds EM78P809N Oscillator Type Frequency Mode C1 pF C2 pFExt. Clock 740 Crystal/Resonator-Parallel Mode Circuit External RC Oscillator Mode Code Option Register Enwdtb = 0 Enable Enwdtb = 1 DisableCode Option Register Word For design reference only External Power-on Reset Circuit Power-on ConsiderationsCustomer ID Register Cyes = 0 One cycle Cyes = 1 Two cycles Vdd Residue-Voltage ProtectionEM78P809N Rin Vdd EM78P809N Vdd 40KR2 Instruction Set DEC Binary Instruction Hex Mnemonic Operation Status Affected Absolute Maximum Ratings Symbol Parameter Condition Min Typ Max UnitRecommended Operating Conditions Vss = Ta= 25 C, VDD= 5.0V ± 5%, VSS= DC Electrical CharacteristicsTypical value is based on characterization results at 25C Ta= 25 C, VDD= 3.0V ± 5%, VSS= Varef Symbol Parameter Conditions Min Typ Max Unit AC Electrical CharacteristicTa=- 40C ~ 85 C, VDD=5V ± 5%, VSS=0V = selected prescaler ratio AC Test Input/Output Waveform Timing Diagram OTP MCU Package TypesPin Count Package Size Contents III EM78P809N