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IBM EM78P809N manual SPIC2 − SPI Control Register 2 Address 06h, Spid SPI Data Buffer Address 07h

Models: EM78P809N

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EM78P809N

8-Bit Microcontroller

Bit 0 ( WBE ) : Write buffer empty flag. Read only.

WBE = “0” : Write buffer empty

WBE = “1” : Not empty, set to “1” automatically when writing data to the data buffer.

SPIC2 − SPI Control Register 2 (Address : 06h )

Bit 7	Bit 6	Bit 5	Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

SPIS

0

0

0

0

SPIM1

SPIM0

RBF

Bit 7 ( SPIS ) : SPI start shift, set the bit to “1” and shift register starts to shift. It is cleared by hardware when shifting is finished. In transferring the next data, it must be set to “1” again.

SPIS = “0” : Shift finish

SPIS = “1” : Shift starts

Bit 2 ~ Bit 1 ( SPIM1 ~ SPIM0) : SPI Transfer Mode Select

TC2CK1	TC2CK0		Transfer Mode
0	0		8-bit Transmit/Receive mode

0	1		8-bit Transmit mode

1	0		8-bit Receive mode

1	1		Reserved

Bit 0 ( RBF ) : Set to 1 by Buffer Full Detector, and cleared to 0 automatically when reading data from the SPID register. RBF bit will be cleared by hardware when enabling SPI. And RBF bit is read-only. Therefore, reading the SPRL register is necessary to avoid data collision to occur (DCOL).

SPID (SPI Data Buffer ( Address: 07h )

Bit 7		Bit 6	Bit 5	Bit 4		Bit 3		Bit 2	Bit 1		Bit 0
Bit 7		Bit 6	Bit 5	Bit 4		Bit 3		Bit 2	Bit 1		Bit 0

SPID7		SPID6	SPID5	SPID4		SPID3		SPID2	SPID1		SPID0

Bit 7 ~ Bit 0 ( SPID7 ~ SPID0 ) : SPI data buffer.

PHC1 − Pull High Control Register 1 ( Address: 0Ah )

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

-

-

/PHE81 /PHE80 /PHE63 /PHE62 /PHE61

/PHE60

Bit 5 ~ 4 ( /PHE81 ~ /PHE80 ) : bits 1, 0 of Port 8 Pull high enable bit

/PHE8x = “0” : Enable P8x pull high

/PHE8x = “1” : Disable P8x pull high

Product Specification (V1.0) 07.26.2005

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(This specification is subject to change without further notice)

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IBM EM78P809N manual SPIC2 − SPI Control Register 2 Address 06h, Spid SPI Data Buffer Address 07h, Transfer Mode

Contents

DOC. Version EM78P809NElan Microelectronics Corporation Contents Specification Revision History Bit Microcontroller CPU„ General purpose ApplicationsPin Assignment OTP Programming Pins Function Description Functional Block DiagramTbktc Operating RegistersR2/PC − Program Counter & Stack Address 02h R1/TCC − Time Clock /Counter Address 01hBit 7 ~ Bit 6 RBS1 ~ RBS0 R-Register page select R3/SR − Status Register Address 03hBit 5 Not used RBS1 RBS0GRBS1 GRBS0 Bit 0 C Carry flag R4/RSR − RAM Select Register Address 04hGeneral Purpose Register Bank Address 20H ~ 3FH PORT6 − Port 6 I/O Data Register Address 06h SIS = 0 Idle mode SIS = 1 Sleep modePORT7 Port 7 I/O Data Register Address 07h PORT8 − Port 8 I/O Data Register Address 08hTC4S = 1 Start TC4CR Timer/Counter 4 Control Register Address 0BhTC4FF1 TC4FF0 TC4CK2 TC4CK1 TC4CK0ISFR1 − Interrupt Status Flag Register 1 Address 0Eh Bit Microcontroller TC4D − Timer 4 Data Buffer Address 0ChTC3CAP = Bit 7 TC3CAP Software capture controlTC3S = 1 Start TC3CAP TC3S TC3CK1 TC3CK0 TC3MTC2M = 1 Window mode TC3DB − Timer 3 Data Buffer B Address 07hBit 7 ~ Bit 6 ADD1 ~ ADD0 AD low 2-bit data buffer TC2S = 1 StartTC2DL − Timer 2 Data Buffer Low Byte Address 0Ah TC2DH − Timer 2 Data Buffer High Byte Address 09hAdcr − AD Control Register Address 0Bh Bit 7 ~ Bit 0 ADE7 ~ ADE0 AD input pin enable control Bit 3 ADP AD power controlAdic − AD Input Pin Control Address 0Ch Addh − AD High 8-bit Data Buffer Address 0DhTEN = 0 Disable TEN = 1 Enable Bit 7 TEN Keytone enable controlBit 3 Tbten Time Base Timer Enable Control Bit Microcontroller Tbktc − TBT/Keytone Control Address 0EhUinven = 0 Disable TXD and RXD port inverse output Bit 3 Uinven Enable Uart TXD and RXD port inverse outputUinven = 1 Enable TXD and RXD port inverse output Bit 4 ~ Bit 2 BRATE2 ~ BRATE1 Transmit Baud Rate SelectBit Microcontroller URS − Uart Status Register Address 07h Bit 5 PRE Enable parity additionEven = 0 Odd parity Even = 1 Even parity EDS = 0 Rising edge EDS = 1 Falling edge Bit 2 EDS Data shift out edge selectSMP Dcol BRS2 BRS1 EDS Dord WBESPIC2 − SPI Control Register 2 Address 06h Transfer ModeSpid SPI Data Buffer Address 07h SPID7 SPID6 SPID5 SPID4 SPID3 SPID2 SPID1 SPID0PLC1 Pull Low Control Register 1 Address 0Bh PLE7x = 1 Disable P7x pull lowPHC2 − Pull High Control Register 2 Address 0Ch PLC2 − Pull Low Control 2 Address 0DhAccumulator Special Purpose RegistersControl Register Bit 7 Wdto WDT output selectIntcr − INT Control Register Address 0Bh Bit Microcontroller IOC6 ~ IOC9 − I/O Port Control RegisterBit 2 Reserved INT1ES = 0 Rising edge INT1ES = 1 Falling edgeExternal Interrupt INT Pin Secondary Enable Condition Function PinAdoscr − AD Offset Control Register Address 0Ch EdgeUerrie Urie Utie Tbie EXIE1 TCIE0 IMR2 − Interrupt Mask Register 2 Address 0FhRegisters for CPU operation mode CPU Operation ModeRbank Register Bank bits 7, 6 of R3, R/W Read/Write RbankOperation Mode Mode Switching ControlNormal → Don’t care → Interrupt request flag will be recorded AD ConverterRegisters for AD Converter Circuit Sampling Time ADC Data RegisterConversion Time ADCK10 Time Base Timer and Keytone GeneratorMax. Frequency Max. Conversion Rate per Bit Tone Output Pin Timing Chart Registers for Uart Circuit Uart Universal Asynchronous Receiver/TransmitterRbank Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit Data Format in Uart Uart ModeReceiving TransmittingBaud Rate Generator SPI Serial Peripheral InterfaceRegisters for the SPI Circuit Transfer Mode Shift Direction and Sample PhaseBit Transmit Mode Serial ClockBit Transmit/Receive Mode Bit Microcontroller Bit Receive ModeMultiple Device Connect /SS SCK pinRegisters for Timer/Counter 2 Circuit Timer/CounterRbank Address Name Bit 7 Bit 6 Bit Counter Mode Timer ModeWindow Mode Registers for Timer/Counter 3 Circuit Window Mode Timing ChartConfiguration of Timer/Counter3 Capture modeTCIF4 Registers for Timer 4 CircuitTCR4 PDO Mode12 TCC/WDT & Prescaler PWM ModeTC4 Interrupt Reset Reset and Wake-up13 I/O Ports Wake-up from Idle mode Wake-up from Sleep ModeAll interrupt Summary of the Initialized Values for Registers Address Name Reset Type BitSCR Bit Microcontroller Register BankTC2D9 TC2D8 Register Bank Reset Type Previous value before resetStatus of RST, T, and P of Status Register Bit Microcontroller General Purpose RegistersInterrupt Controller Reset Block DiagramOscillator Modes OscillatorCrystal Oscillator/Ceramic Resonators Crystal Summary of Maximum Operating SpeedsEM78P809N Oscillator Type Frequency Mode C1 pF C2 pFExt. Clock 740Crystal/Resonator-Parallel Mode Circuit External RC Oscillator ModeCode Option Register Enwdtb = 0 Enable Enwdtb = 1 DisableCode Option Register Word For design reference onlyExternal Power-on Reset Circuit Power-on ConsiderationsCustomer ID Register Cyes = 0 One cycle Cyes = 1 Two cyclesVdd Residue-Voltage ProtectionEM78P809N Rin Vdd EM78P809NVdd 40KR2 Instruction SetDEC Binary Instruction Hex Mnemonic Operation Status AffectedAbsolute Maximum Ratings Symbol Parameter Condition Min Typ Max UnitRecommended Operating Conditions Vss =Ta= 25 C, VDD= 5.0V ± 5%, VSS= DC Electrical CharacteristicsTypical value is based on characterization results at 25C Ta= 25 C, VDD= 3.0V ± 5%, VSS= Varef Symbol Parameter Conditions Min Typ Max Unit AC Electrical CharacteristicTa=- 40C ~ 85 C, VDD=5V ± 5%, VSS=0V = selected prescaler ratioAC Test Input/Output Waveform Timing DiagramOTP MCU Package TypesPin Count Package Size Contents III EM78P809N