Transmitting, Receiving | IBM EM78P809N guide

EM78P809N

8-Bit Microcontroller

4.7.2 Transmitting:

In transmitting serial data, the UART operates as follows:

1.Set the TXE bit of the URC1 register to enable the UART transmission function.

2.Write data into the URTD register and the UTBE bit of the URC1 register will be set by hardware.

3.Then start transmitting.

4.Serially transmitted data are transmitted in the following order from the TX pin.

5.Start bit: one “0” bit is output.

6.Transmit data: 7, 8 or 9 bits data are output from the LSB to the MSB.

7.Parity bit: one parity bit (odd or even selectable) is output.

8.Stop bit: one “1” bit (stop bit) is output.

Mark state: output “1” continues until the start bit of the next transmitted data.

After transmitting the stop bit, the UART generates a TBEF interrupt (if enabled).

4.7.3 Receiving:

In receiving, the UART operates as follows:

1.Set RXE bit of the URS register to enable the UART receiving function.

The UART monitors the RX pin and synchronizes internally when it detects a start bit.

2.Receive data is shifted into the URRD register in the order from LSB to MSB.

3.The parity bit and the stop bit are received.

After one character received, the UART generates a RBFF interrupt (if enable). And URBF bit of URS register will be set to 1.

4.The UART makes the following checks:

(a)Parity check: The number of 1 of the received data must match the even or odd parity setting of the EVEN bit in the URS register.

(b)Frame check: The start bit must be 0 and the stop bit must be 1.

(c)Overrun check: The URBF bit of the URS register must be cleared (that means the URRD register should be read out) before next received data is loaded into the URRD register.

If any checks failed, the UERRIF interrupt will be generated (if enabled), and an error flag is indicated in PRERR, OVERR or FMERR bit. The error flag should be cleared by software else the UERRIF interrupt will occur when the next byte is received.

5.Read received data from URRD register. And URBF bit will be clear by hardware.

Product Specification (V1.0) 07.26.2005

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(This specification is subject to change without further notice)

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IBM EM78P809N manual Transmitting, Receiving

Contents

DOC. Version EM78P809N Elan Microelectronics Corporation Contents Specification Revision History Bit Microcontroller CPU „ General purpose Applications Pin Assignment OTP Programming Pins Function Description Functional Block Diagram Tbktc Operating Registers R2/PC − Program Counter & Stack Address 02h R1/TCC − Time Clock /Counter Address 01h RBS1 RBS0 R3/SR − Status Register Address 03hBit 7 ~ Bit 6 RBS1 ~ RBS0 R-Register page select Bit 5 Not used Bit 0 C Carry flag R4/RSR − RAM Select Register Address 04h GRBS1 GRBS0General Purpose Register Bank Address 20H ~ 3FH PORT8 − Port 8 I/O Data Register Address 08h SIS = 0 Idle mode SIS = 1 Sleep modePORT6 − Port 6 I/O Data Register Address 06h PORT7 Port 7 I/O Data Register Address 07h TC4CK2 TC4CK1 TC4CK0 TC4CR Timer/Counter 4 Control Register Address 0BhTC4S = 1 Start TC4FF1 TC4FF0 ISFR1 − Interrupt Status Flag Register 1 Address 0Eh Bit Microcontroller TC4D − Timer 4 Data Buffer Address 0Ch TC3CAP TC3S TC3CK1 TC3CK0 TC3M Bit 7 TC3CAP Software capture controlTC3CAP = TC3S = 1 Start TC2S = 1 Start TC3DB − Timer 3 Data Buffer B Address 07hTC2M = 1 Window mode Bit 7 ~ Bit 6 ADD1 ~ ADD0 AD low 2-bit data buffer TC2DH − Timer 2 Data Buffer High Byte Address 09h TC2DL − Timer 2 Data Buffer Low Byte Address 0AhAdcr − AD Control Register Address 0Bh Addh − AD High 8-bit Data Buffer Address 0Dh Bit 3 ADP AD power controlBit 7 ~ Bit 0 ADE7 ~ ADE0 AD input pin enable control Adic − AD Input Pin Control Address 0Ch Bit Microcontroller Tbktc − TBT/Keytone Control Address 0Eh Bit 7 TEN Keytone enable controlTEN = 0 Disable TEN = 1 Enable Bit 3 Tbten Time Base Timer Enable Control Bit 4 ~ Bit 2 BRATE2 ~ BRATE1 Transmit Baud Rate Select Bit 3 Uinven Enable Uart TXD and RXD port inverse outputUinven = 0 Disable TXD and RXD port inverse output Uinven = 1 Enable TXD and RXD port inverse output Bit 5 PRE Enable parity addition Bit Microcontroller URS − Uart Status Register Address 07hEven = 0 Odd parity Even = 1 Even parity EDS Dord WBE Bit 2 EDS Data shift out edge selectEDS = 0 Rising edge EDS = 1 Falling edge SMP Dcol BRS2 BRS1 SPID7 SPID6 SPID5 SPID4 SPID3 SPID2 SPID1 SPID0 Transfer ModeSPIC2 − SPI Control Register 2 Address 06h Spid SPI Data Buffer Address 07h PLC2 − Pull Low Control 2 Address 0Dh PLE7x = 1 Disable P7x pull lowPLC1 Pull Low Control Register 1 Address 0Bh PHC2 − Pull High Control Register 2 Address 0Ch Bit 7 Wdto WDT output select Special Purpose RegistersAccumulator Control Register INT1ES = 0 Rising edge INT1ES = 1 Falling edge Bit Microcontroller IOC6 ~ IOC9 − I/O Port Control RegisterIntcr − INT Control Register Address 0Bh Bit 2 Reserved Edge INT Pin Secondary Enable Condition Function PinExternal Interrupt Adoscr − AD Offset Control Register Address 0Ch Uerrie Urie Utie Tbie EXIE1 TCIE0 IMR2 − Interrupt Mask Register 2 Address 0Fh Rbank CPU Operation ModeRegisters for CPU operation mode Rbank Register Bank bits 7, 6 of R3, R/W Read/Write Mode Switching Control Operation ModeNormal AD Converter → Don’t care → Interrupt request flag will be recordedRegisters for AD Converter Circuit ADC Data Register Sampling TimeConversion Time Time Base Timer and Keytone Generator ADCK10Max. Frequency Max. Conversion Rate per Bit Tone Output Pin Timing Chart Uart Universal Asynchronous Receiver/Transmitter Registers for Uart CircuitRbank Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit Data Format in Uart Uart Mode Receiving Transmitting SPI Serial Peripheral Interface Baud Rate GeneratorRegisters for the SPI Circuit Serial Clock Shift Direction and Sample PhaseTransfer Mode Bit Transmit Mode Bit Transmit/Receive Mode Bit Microcontroller Bit Receive Mode Multiple Device Connect /SS SCK pin Timer/Counter Registers for Timer/Counter 2 CircuitRbank Address Name Bit 7 Bit 6 Bit Timer Mode Counter ModeWindow Mode Registers for Timer/Counter 3 Circuit Window Mode Timing Chart Configuration of Timer/Counter3 Capture mode TCIF4 Registers for Timer 4 Circuit TCR4 PDO Mode PWM Mode 12 TCC/WDT & PrescalerTC4 Interrupt Reset and Wake-up Reset13 I/O Ports Wake-up from Sleep Mode Wake-up from Idle modeAll interrupt Summary of the Initialized Values for Registers Address Name Reset Type Bit SCR Bit Microcontroller Register Bank TC2D9 TC2D8 Register Bank Bit Microcontroller General Purpose Registers Previous value before resetReset Type Status of RST, T, and P of Status Register Interrupt Controller Reset Block Diagram Summary of Maximum Operating Speeds OscillatorOscillator Modes Crystal Oscillator/Ceramic Resonators Crystal 740 Oscillator Type Frequency Mode C1 pF C2 pFEM78P809N Ext. Clock Crystal/Resonator-Parallel Mode Circuit External RC Oscillator Mode For design reference only Enwdtb = 0 Enable Enwdtb = 1 DisableCode Option Register Code Option Register Word Cyes = 0 One cycle Cyes = 1 Two cycles Power-on ConsiderationsExternal Power-on Reset Circuit Customer ID Register Vdd EM78P809N Residue-Voltage ProtectionVdd EM78P809N Rin Vdd 40KR2 Instruction Set DEC Binary Instruction Hex Mnemonic Operation Status Affected Vss = Symbol Parameter Condition Min Typ Max UnitAbsolute Maximum Ratings Recommended Operating Conditions DC Electrical Characteristics Ta= 25 C, VDD= 5.0V ± 5%, VSS=Typical value is based on characterization results at 25C Ta= 25 C, VDD= 3.0V ± 5%, VSS= Varef = selected prescaler ratio AC Electrical CharacteristicSymbol Parameter Conditions Min Typ Max Unit Ta=- 40C ~ 85 C, VDD=5V ± 5%, VSS=0V AC Test Input/Output Waveform Timing Diagram Package Types OTP MCUPin Count Package Size Contents III EM78P809N