Wake-up from Sleep Mode, Wake-up from Idle mode | IBM EM78P809N

EM78P809N

8-Bit Microcontroller

The Watchdog timer and prescaler are cleared.

Upon power on, the upper 2 bits of R3 are cleared.

Upon power on, the upper 2 bits of R4 are cleared.

Upon power on, the upper 3 bits of R5 are cleared.

The bits of CONT register are set to all “1” except bit 6 (INT flag).

ISFR0, ISFR1, ISFR2 register and IMR1, IMR2 registers are cleared. The controller has two modes for power saving.

(1) SLEEP mode: R5 (SIS) = 1, SLEP instruction.

The internal oscillator is turned off and all system operation is halted.

(2) IDLE mode: R5 (SIS)= 0, SLEP instruction

The CPU core halts but the on-chip peripheral and oscillator circuit remain active.

4.14.2 Wake-up from SLEEP Mode:

(1) External /SLEEP pin

The controller will be waken up and execute the next instruction after entering SLEEP mode. All the registers will maintain their original values before “SLEP” instruction was executed.

(2) /RESET pin pull low

This will reset the controller and starts the program at address zero.

(3) WDT time out

This will reset the controller and run the program at address zero.

4.14.3 Wake-up from IDLE mode:

(1) All interrupt

In all these cases, user should always enable the circuit before entering IDLE mode. After wake-up, all registers will maintain their original values before entering “SLEP” instruction, then service an interrupt subroutine or proceed with next instruction by setting individual interrupt enable bit. After servicing an interrupt sub-routine (“RETI” instruction), the program will jump from “SLEP” instruction to the next instruction.

(2) /RESET pin pull low

This will reset the controller and run the program at address zero.

(3) WDT time out

This will reset the controller and run the program at address zero.

48 •	Product Specification (V1.0) 07.26.2005

(This specification is subject to change without further notice)

Image 52

IBM EM78P809N manual Wake-up from Sleep Mode, Wake-up from Idle mode, All interrupt

Contents

EM78P809N DOC. Version Elan Microelectronics Corporation Contents Specification Revision History CPU Bit Microcontroller Applications „ General purpose Pin Assignment OTP Programming Pins Functional Block Diagram Function Description Operating Registers Tbktc R1/TCC − Time Clock /Counter Address 01h R2/PC − Program Counter & Stack Address 02h R3/SR − Status Register Address 03h Bit 7 ~ Bit 6 RBS1 ~ RBS0 R-Register page selectBit 5 Not used RBS1 RBS0 GRBS1 GRBS0 Bit 0 C Carry flag R4/RSR − RAM Select Register Address 04hGeneral Purpose Register Bank Address 20H ~ 3FH SIS = 0 Idle mode SIS = 1 Sleep mode PORT6 − Port 6 I/O Data Register Address 06hPORT7 Port 7 I/O Data Register Address 07h PORT8 − Port 8 I/O Data Register Address 08h TC4CR Timer/Counter 4 Control Register Address 0Bh TC4S = 1 StartTC4FF1 TC4FF0 TC4CK2 TC4CK1 TC4CK0 Bit Microcontroller TC4D − Timer 4 Data Buffer Address 0Ch ISFR1 − Interrupt Status Flag Register 1 Address 0Eh Bit 7 TC3CAP Software capture control TC3CAP =TC3S = 1 Start TC3CAP TC3S TC3CK1 TC3CK0 TC3M TC3DB − Timer 3 Data Buffer B Address 07h TC2M = 1 Window modeBit 7 ~ Bit 6 ADD1 ~ ADD0 AD low 2-bit data buffer TC2S = 1 Start TC2DL − Timer 2 Data Buffer Low Byte Address 0Ah TC2DH − Timer 2 Data Buffer High Byte Address 09hAdcr − AD Control Register Address 0Bh Bit 3 ADP AD power control Bit 7 ~ Bit 0 ADE7 ~ ADE0 AD input pin enable controlAdic − AD Input Pin Control Address 0Ch Addh − AD High 8-bit Data Buffer Address 0Dh Bit 7 TEN Keytone enable control TEN = 0 Disable TEN = 1 EnableBit 3 Tbten Time Base Timer Enable Control Bit Microcontroller Tbktc − TBT/Keytone Control Address 0Eh Bit 3 Uinven Enable Uart TXD and RXD port inverse output Uinven = 0 Disable TXD and RXD port inverse outputUinven = 1 Enable TXD and RXD port inverse output Bit 4 ~ Bit 2 BRATE2 ~ BRATE1 Transmit Baud Rate Select Bit Microcontroller URS − Uart Status Register Address 07h Bit 5 PRE Enable parity additionEven = 0 Odd parity Even = 1 Even parity Bit 2 EDS Data shift out edge select EDS = 0 Rising edge EDS = 1 Falling edgeSMP Dcol BRS2 BRS1 EDS Dord WBE Transfer Mode SPIC2 − SPI Control Register 2 Address 06hSpid SPI Data Buffer Address 07h SPID7 SPID6 SPID5 SPID4 SPID3 SPID2 SPID1 SPID0 PLE7x = 1 Disable P7x pull low PLC1 Pull Low Control Register 1 Address 0BhPHC2 − Pull High Control Register 2 Address 0Ch PLC2 − Pull Low Control 2 Address 0Dh Special Purpose Registers AccumulatorControl Register Bit 7 Wdto WDT output select Bit Microcontroller IOC6 ~ IOC9 − I/O Port Control Register Intcr − INT Control Register Address 0BhBit 2 Reserved INT1ES = 0 Rising edge INT1ES = 1 Falling edge INT Pin Secondary Enable Condition Function Pin External InterruptAdoscr − AD Offset Control Register Address 0Ch Edge IMR2 − Interrupt Mask Register 2 Address 0Fh Uerrie Urie Utie Tbie EXIE1 TCIE0 CPU Operation Mode Registers for CPU operation modeRbank Register Bank bits 7, 6 of R3, R/W Read/Write Rbank Operation Mode Mode Switching ControlNormal → Don’t care → Interrupt request flag will be recorded AD ConverterRegisters for AD Converter Circuit Sampling Time ADC Data RegisterConversion Time ADCK10 Time Base Timer and Keytone GeneratorMax. Frequency Max. Conversion Rate per Bit Tone Output Pin Timing Chart Registers for Uart Circuit Uart Universal Asynchronous Receiver/TransmitterRbank Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit Uart Mode Data Format in Uart Transmitting Receiving Baud Rate Generator SPI Serial Peripheral InterfaceRegisters for the SPI Circuit Shift Direction and Sample Phase Transfer ModeBit Transmit Mode Serial Clock Bit Microcontroller Bit Receive Mode Bit Transmit/Receive Mode SCK pin Multiple Device Connect /SS Registers for Timer/Counter 2 Circuit Timer/CounterRbank Address Name Bit 7 Bit 6 Bit Counter Mode Timer ModeWindow Mode Window Mode Timing Chart Registers for Timer/Counter 3 Circuit Capture mode Configuration of Timer/Counter3 Registers for Timer 4 Circuit TCIF4 PDO Mode TCR4 12 TCC/WDT & Prescaler PWM ModeTC4 Interrupt Reset Reset and Wake-up13 I/O Ports Wake-up from Idle mode Wake-up from Sleep ModeAll interrupt Address Name Reset Type Bit Summary of the Initialized Values for Registers Bit Microcontroller Register Bank SCR TC2D9 TC2D8 Register Bank Previous value before reset Reset TypeStatus of RST, T, and P of Status Register Bit Microcontroller General Purpose Registers Controller Reset Block Diagram Interrupt Oscillator Oscillator ModesCrystal Oscillator/Ceramic Resonators Crystal Summary of Maximum Operating Speeds Oscillator Type Frequency Mode C1 pF C2 pF EM78P809NExt. Clock 740 External RC Oscillator Mode Crystal/Resonator-Parallel Mode Circuit Enwdtb = 0 Enable Enwdtb = 1 Disable Code Option RegisterCode Option Register Word For design reference only Power-on Considerations External Power-on Reset CircuitCustomer ID Register Cyes = 0 One cycle Cyes = 1 Two cycles Residue-Voltage Protection VddEM78P809N Rin Vdd EM78P809N Instruction Set Vdd 40KR2 Binary Instruction Hex Mnemonic Operation Status Affected DEC Symbol Parameter Condition Min Typ Max Unit Absolute Maximum RatingsRecommended Operating Conditions Vss = Ta= 25 C, VDD= 5.0V ± 5%, VSS= DC Electrical CharacteristicsTypical value is based on characterization results at 25C Ta= 25 C, VDD= 3.0V ± 5%, VSS= Varef AC Electrical Characteristic Symbol Parameter Conditions Min Typ Max UnitTa=- 40C ~ 85 C, VDD=5V ± 5%, VSS=0V = selected prescaler ratio Timing Diagram AC Test Input/Output Waveform OTP MCU Package TypesPin Count Package Size Contents III EM78P809N