Capture mode, Configuration of Timer/Counter3 | IBM EM78P809N

		Rising	Inhibit
	Edge	Falling	Capture
	Detector	Falling	Control
	INT3ES
	TC3M
TC3 pin	M
	M
fc/2 12 , fs/2 4	MUX
fc/210, fs/22
fc/27
		TC3S
	TC2CK
		CAP
	2
		Capture
	TC3CR		TCR3B

EM78P809N

8-Bit Microcontroller

TC3

Interrupt

Overflow

8-bit Up-counter

Comparator

Capture

TCR3A

Fig. 23. Configuration of Timer/Counter3

4.10.1 Timer Mode:

In Timer mode, counting up is performed using the internal clock. When the contents of the up-counter matched with the TCR3DA, then interrupt is generated and the counter is cleared. Counting up resumes after the counter is cleared. The current contents of the up-counter are loaded into the TCR3DB by setting TC3CAP to “1” and the TC3CAP is cleared to “0” after capture automatically.

4.10.2Counter Mode:

In Counter mode, counting up is performed using the external clock input pin (TC3 pin) and either rising or falling edge can be selected by INT3ES0 but both edge cannot be used. When the contents of the up-counter matched with the TCR3DA, then interrupt is generated and the counter is cleared. Counting up resumes after the counter is cleared. The current contents of the up-counter are loaded into the TCR3DB by setting TC3CAP to “1” and the TC3CAP is cleared to “0” after capture automatically.

4.10.3Capture mode:

In Capture mode, the pulse width, period and duty of the TC3 input pin are measured in this mode, which can be used in decoding the remote control signal. The counter is free running by the internal clock. On the rising (falling) edge of TC3 pin input, the contents of the counter is loaded into TCR3DA, then the counter is cleared and interrupt is generated. On the falling (rising) edge of TC3 pin input, the contents of the counter are loaded into TCR3DB. The counter is still counting, on the next rising edge of the TC3 pin input, the contents of the counter are loaded into TCR3A, counter is

Product Specification (V1.0) 07.26.2005

• 43

(This specification is subject to change without further notice)

Image 47

IBM EM78P809N manual Capture mode, Configuration of Timer/Counter3

Contents

DOC. Version EM78P809N Elan Microelectronics Corporation Contents Specification Revision History Bit Microcontroller CPU „ General purpose Applications Pin Assignment OTP Programming Pins Function Description Functional Block Diagram Tbktc Operating Registers R2/PC − Program Counter & Stack Address 02h R1/TCC − Time Clock /Counter Address 01h RBS1 RBS0 R3/SR − Status Register Address 03hBit 7 ~ Bit 6 RBS1 ~ RBS0 R-Register page select Bit 5 Not used General Purpose Register Bank Address 20H ~ 3FH Bit 0 C Carry flag R4/RSR − RAM Select Register Address 04hGRBS1 GRBS0 PORT8 − Port 8 I/O Data Register Address 08h SIS = 0 Idle mode SIS = 1 Sleep modePORT6 − Port 6 I/O Data Register Address 06h PORT7 Port 7 I/O Data Register Address 07h TC4CK2 TC4CK1 TC4CK0 TC4CR Timer/Counter 4 Control Register Address 0BhTC4S = 1 Start TC4FF1 TC4FF0 ISFR1 − Interrupt Status Flag Register 1 Address 0Eh Bit Microcontroller TC4D − Timer 4 Data Buffer Address 0Ch TC3CAP TC3S TC3CK1 TC3CK0 TC3M Bit 7 TC3CAP Software capture controlTC3CAP = TC3S = 1 Start TC2S = 1 Start TC3DB − Timer 3 Data Buffer B Address 07hTC2M = 1 Window mode Bit 7 ~ Bit 6 ADD1 ~ ADD0 AD low 2-bit data buffer Adcr − AD Control Register Address 0Bh TC2DH − Timer 2 Data Buffer High Byte Address 09hTC2DL − Timer 2 Data Buffer Low Byte Address 0Ah Addh − AD High 8-bit Data Buffer Address 0Dh Bit 3 ADP AD power controlBit 7 ~ Bit 0 ADE7 ~ ADE0 AD input pin enable control Adic − AD Input Pin Control Address 0Ch Bit Microcontroller Tbktc − TBT/Keytone Control Address 0Eh Bit 7 TEN Keytone enable controlTEN = 0 Disable TEN = 1 Enable Bit 3 Tbten Time Base Timer Enable Control Bit 4 ~ Bit 2 BRATE2 ~ BRATE1 Transmit Baud Rate Select Bit 3 Uinven Enable Uart TXD and RXD port inverse outputUinven = 0 Disable TXD and RXD port inverse output Uinven = 1 Enable TXD and RXD port inverse output Even = 0 Odd parity Even = 1 Even parity Bit 5 PRE Enable parity additionBit Microcontroller URS − Uart Status Register Address 07h EDS Dord WBE Bit 2 EDS Data shift out edge selectEDS = 0 Rising edge EDS = 1 Falling edge SMP Dcol BRS2 BRS1 SPID7 SPID6 SPID5 SPID4 SPID3 SPID2 SPID1 SPID0 Transfer ModeSPIC2 − SPI Control Register 2 Address 06h Spid SPI Data Buffer Address 07h PLC2 − Pull Low Control 2 Address 0Dh PLE7x = 1 Disable P7x pull lowPLC1 Pull Low Control Register 1 Address 0Bh PHC2 − Pull High Control Register 2 Address 0Ch Bit 7 Wdto WDT output select Special Purpose RegistersAccumulator Control Register INT1ES = 0 Rising edge INT1ES = 1 Falling edge Bit Microcontroller IOC6 ~ IOC9 − I/O Port Control RegisterIntcr − INT Control Register Address 0Bh Bit 2 Reserved Edge INT Pin Secondary Enable Condition Function PinExternal Interrupt Adoscr − AD Offset Control Register Address 0Ch Uerrie Urie Utie Tbie EXIE1 TCIE0 IMR2 − Interrupt Mask Register 2 Address 0Fh Rbank CPU Operation ModeRegisters for CPU operation mode Rbank Register Bank bits 7, 6 of R3, R/W Read/Write Normal Mode Switching ControlOperation Mode Registers for AD Converter Circuit AD Converter→ Don’t care → Interrupt request flag will be recorded Conversion Time ADC Data RegisterSampling Time Max. Frequency Max. Conversion Rate per Bit Time Base Timer and Keytone GeneratorADCK10 Tone Output Pin Timing Chart Rbank Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit Uart Universal Asynchronous Receiver/TransmitterRegisters for Uart Circuit Data Format in Uart Uart Mode Receiving Transmitting Registers for the SPI Circuit SPI Serial Peripheral InterfaceBaud Rate Generator Serial Clock Shift Direction and Sample PhaseTransfer Mode Bit Transmit Mode Bit Transmit/Receive Mode Bit Microcontroller Bit Receive Mode Multiple Device Connect /SS SCK pin Rbank Address Name Bit 7 Bit 6 Bit Timer/CounterRegisters for Timer/Counter 2 Circuit Window Mode Timer ModeCounter Mode Registers for Timer/Counter 3 Circuit Window Mode Timing Chart Configuration of Timer/Counter3 Capture mode TCIF4 Registers for Timer 4 Circuit TCR4 PDO Mode TC4 Interrupt PWM Mode12 TCC/WDT & Prescaler 13 I/O Ports Reset and Wake-upReset All interrupt Wake-up from Sleep ModeWake-up from Idle mode Summary of the Initialized Values for Registers Address Name Reset Type Bit SCR Bit Microcontroller Register Bank TC2D9 TC2D8 Register Bank Bit Microcontroller General Purpose Registers Previous value before resetReset Type Status of RST, T, and P of Status Register Interrupt Controller Reset Block Diagram Summary of Maximum Operating Speeds OscillatorOscillator Modes Crystal Oscillator/Ceramic Resonators Crystal 740 Oscillator Type Frequency Mode C1 pF C2 pFEM78P809N Ext. Clock Crystal/Resonator-Parallel Mode Circuit External RC Oscillator Mode For design reference only Enwdtb = 0 Enable Enwdtb = 1 DisableCode Option Register Code Option Register Word Cyes = 0 One cycle Cyes = 1 Two cycles Power-on ConsiderationsExternal Power-on Reset Circuit Customer ID Register Vdd EM78P809N Residue-Voltage ProtectionVdd EM78P809N Rin Vdd 40KR2 Instruction Set DEC Binary Instruction Hex Mnemonic Operation Status Affected Vss = Symbol Parameter Condition Min Typ Max UnitAbsolute Maximum Ratings Recommended Operating Conditions Typical value is based on characterization results at 25C DC Electrical CharacteristicsTa= 25 C, VDD= 5.0V ± 5%, VSS= Ta= 25 C, VDD= 3.0V ± 5%, VSS= Varef = selected prescaler ratio AC Electrical CharacteristicSymbol Parameter Conditions Min Typ Max Unit Ta=- 40C ~ 85 C, VDD=5V ± 5%, VSS=0V AC Test Input/Output Waveform Timing Diagram Pin Count Package Size Package TypesOTP MCU Contents III EM78P809N