Networking Silicon — 82540EP
Datasheet 5
2.0 Features of the 82540EP Gigabit Ethernet Controller
2.1 PCI Features
2.2 MAC Specific Features
Features Benefits
PCI Revision 2.3 support for 32-bit wide interface at
33 MHz and 66 MHz
• Application flexibility for LAN on Motherboard
(LOM) or embedded sol utions
• 64-bit addressing for systems wi th more than 4
Gigabytes of physical memory
• Support for new PCI 2.3 inter rupt status/contr ol
Algorithms that optimally use advanced PCI, MWI,
MRM, and MRL commands • Efficient bus operations
CardBus Information Services (CIS) Pointer • Enables CardBus operatio n ( when used with
external FLASH de vice and series termination on
PCI bus)
CLKRUN# Signal • PCI clock suspension for low power mobile design
Features Benefits
Low-latency transmit and receive queues • Network packets handled without waiting or buffer
overflow.
IEEE 802.3x complia nt flow control suppo rt with
software controllable pause times and thresho ld
values
• Control over the transmissions of pause frames
through software or hardware triggering
• Frame loss reduced from receive over runs
Caches up to 64 packe t descriptors in a single b urst • Efficient use of PC I bandwidth
Programmable host memory receive buffers (256
Bytes to 16 KBytes) and cache line si ze (16 Bytes to
256 Bytes) • Efficient use of PCI bandwidt h
Wide, optimized int ernal data path architecture • Low latency data handling
• Superior DMA transfer rate performance
64 KByte configurable Transmit and Receive FIFO
buffers • No external FIFO memory requirem ents
• FIFO size adjustable to application
Descriptor ring management hardware for transmit
and receive • Simple software programming m odel
Optimized descript or fetching and write-back
mechanisms • Efficient syst em mem o r y and use of PCI
bandwidth
Mechanism available for r educing interrupt s
generated by transmit and recei ve operations • Maximizes system performance and thr o ug hp ut
Support for transmission and reception of packets up
to 16 KBytes • Enables jumbo frames