Signal Type Definitions, PCI Bus Interface | Intel 82540EP manual

Networking Silicon — 82540EP

3.0Signal Descriptions

Note: The targeted signal names are subject to change without notice. Verify with your local Intel sales office that you have the latest information before finalizing a design.

3.1Signal Type Definitions

The signals of the 82540EP controller are electrically defined as follows:

	Name	Definition

	I	Input. Standard input only digital signal.

	O	Output. Standard output only digital signal.

	TS	Tri-state.Bi-directional three-state digital input/output signal.

		Sustained Tri-state.Sustained digital three-state signal driven by one agent at a time.
	STS	An agent driving the STS pin low must actively drive it high for at least one clock before letting it
	STS	float. The next agent of the signal cannot drive the pin earlier than one clock after it has been

		released by the previous agent.

		Open Drain. Wired-OR with other agents.
	OD	The signaling agent asserts the OD signal, but the signal is returned to the inactive state by a
	OD	weak pull-up resistor. The pull-up resistor may require two or three clock periods to fully restore

		the signal to the de-asserted state.

	A	Analog. PHY analog data signal.

	P	Power. Power connection, voltage reference, or other reference connection.

3.2PCI Bus Interface

When the Reset signal (RST#) is asserted, the 82540EP will not drive any PCI output or bi- directional pins except the Power Management Event signal (PME#).

3.2.1PCI Address, Data and Control Signals

Symbol	Type	Name and Function

		Address and Data.
		The address phase is the clock cycle when the Frame signal (FRAME#) is asserted
AD[31:0]		low. During the address phase AD[31:0] contain physical address (32 bits). For I/O,
AD[31:0]		this is byte address, and for configuration and memory, a DWORD address. The
	TS	82540EPbustransactiondeviceincludesusesAddresslittleanendianaddressanddatabytephasesignalsordering.followedaremultiplexedbyoneormoreonthedatasamephasesPCIpins..A
		During data phases, AD[7:0] contain the least significant byte (LSB) and AD[31:24]
		contain the most significant byte (MSB).

Datasheet

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Intel 82540EP manual Signal Type Definitions, PCI Bus Interface, PCI Address, Data and Control Signals, Name Definition

Contents

Revision April 82540EP Gigabit Ethernet Controller Datasheet Date Revision 82540EP Networking Silicon Contents 82540EP Networking Silicon Introduction Acpi LED MdioTX MAC RX MAC Document Scope Reference DocumentsProduct Code 82540EP Networking Silicon Application flexibility for LAN on Motherboard PCI FeaturesMAC Specific Features Features Benefits HostOffloading PHY Specific Features A server management processor Manageability Features Technology Features Additional Device Features PCI Bus Interface Signal Type DefinitionsPCI Address, Data and Control Signals Symbol Type Name and Function TRDY# STS PARFRAME# STS IRDY# STS Error Reporting Signals Arbitration SignalsInterrupt Signal System Signals SMB Signals Eeprom and Serial Flash Interface SignalsPower Management Signals Impedance Compensation Signals Miscellaneous Signals LED SignalsOther Signals Analog XTAL1XTAL2 Analog Supplies Test Interface SignalsPower Supply Connections Digital Supplies CTRL15 Control SignalsGround and No Connects GND Recommended Operating Conditions a Sheet 1 Absolute Maximum RatingsRecommended Operating Conditions Absolute Maximum Ratingsa Recommended Operating Conditions a Sheet 2 DC SpecificationsDC Characteristics Power Specifications D0a Power Specifications D3cold Power Specifications Dr UninitializedPower Specifications Complete Subsystem O Characteristics Symbol Parameter Condition Min Typ Max= V SS AC Characteristics Tcyc Timing Specifications PCI Bus InterfaceSymbol Parameter a PCI 66 MHz PCI 33 MHz Units Min Max PCI Bus Interface Clock Parameters PCI Bus Interface Timing Parameters Symbol Parameter PCI 66MHz PCI 33 MHz Units Min Max VTL Symbol Parameter PCI 66 MHz UnitPCI Bus Interface Timing Measurement Conditions VTH Pin Inch max Point 1kΩ 10 pFInch max Point 50 pF Link Interface Timing Eeprom InterfaceRise and Fall Times Date Code Device Identification82540EP Product Name Yyww Package Information Datasheet Thermal resistance, junction-to-ambient Thermal SpecificationsThermal Characteristics Symbol Parameter Value at specified airflow m/s Units Pinout Information Eeprom and Serial Flash Interface Signals Power Management SignalsImpedance Compensation Signals SMB Signals Analog Power Signals PHY SignalsTest Interface Signals Digital Power Signals Lanpwrgood Smbclk Grounds and No Connect SignalsSignal Names in Pin Order Sheet 1 Signal Name Pin CLKRUN# Smbdata GND Signal Names in Pin Order Sheet 2RST# SMBALRT# M66EN REQ# CBE3# Signal Names in Pin Order Sheet 3 IRDY# FRAME# CBE2# GNDCLK VIO TRDY# Zpcomp Signal Names in Pin Order Sheet 4 STOP# INTA# DEVSEL# ZncompPAR PERR# GNT# Signal Names in Pin Order Sheet 5 CBE1#CBE0# PCIAD5 GND PCIAD1 Clkview FLCE# Eesk Vddo P12 Signal Names in Pin Order Sheet 6PCIAD9 PCIAD7 PCIAD4 PCIAD8 PCIAD6 PCIAD3 PCIAD2 Eecs GND Flso Eedi C D E F G H J K L M N P Visual Pin Reference