Networking Silicon — 82540EP
Datasheet 23
4.5.1.2 PCI Bus Interface Timing
NOTES:
1. Output tim ing measurements are as shown.
2. REQ# and GN T# signals are point -to-point and have di fferent output valid d elay and input setup t imes than
bussed signals. GNT# has a setup of 10 ns; REQ# has a setu p of 12 ns. All other signals ar e bussed.
3. Input timi ng measurements a re as shown.
Table 15. PCI Bus Interface Timing Parameters
Symbol Parameter PCI 66MHz PCI 33 MHz Units
Min Max Min Max
TVAL CLK to signal valid delay: bussed
signals 2 6 2 11 ns
TVAL(ptp) CLK to signal vali d delay: point-
to-point signals 2 6 2 12 ns
TON Float to active delay 2 2 ns
TOFF Active to fl oat delay 14 28 ns
TSU Input setup time to CLK: bussed
signals 37ns
TSU(ptp) Input setup time to CLK: point-to-
point signals 5 10, 12 ns
TH Input hold time from CLK 0 0 ns
TRRSU REQ64# to RST# setup tim e 10*TCYC 10*TCYC ns
TRRH RST # to REQ64# hold time 0 0 ns
Figure 3. PCI Bus Interface O utput Timing Measurement
VTH
VTL
VTEST
PCI_CLK
VTEST
VSTEP (3.3V Signalling)
Output
Delay
Tri-State
Output
output curre nt ≤
leakage current
TONTOFF