Networking Silicon — 82540EP

3.2.2Arbitration Signals

Symbol

Type

Name and Function

 

 

 

REQ#

TS

Request Bus. The Request Bus signal is used to request control of the bus from the

arbiter. This signal is point-to-point.

 

 

 

 

 

GNT#

I

Grant Bus. The Grant Bus signal notifies the 82540EP that bus access has been

granted. This is a point-to-point signal.

 

 

 

 

 

 

 

Lock Bus. The Lock Bus signal is asserted by an initiator to require sole access to a

LOCK#

I

target memory device during two or more separate transfers. The 82540EP device

 

 

does not implement bus locking.

 

 

 

3.2.3Interrupt Signal

Symbol

Type

Name and Function

 

 

 

INTA#

TS

Interrupt A. Interrupt A is used to request an interrupt by port 1 of the 82540EP. It is an

active low, level-triggered interrupt signal.

 

 

 

 

 

3.2.4System Signals

Symbol

Type

 

Name and Function

 

 

 

 

 

 

 

 

PCI Clock.

 

 

CLK

I

82540EPsignal

all

 

 

 

 

 

M66EN

I

66 MHz Enable. M66EN indicates whether the systemthebus

enabled for 66MHz.

 

 

 

 

 

PCI Reset. When the PCI Reset signal is asserted, PCI output signals, except

 

 

Power Management Event

(PME#), are floated and all input signals are ignored.

RST#

I

The PME# context is preserved, depending on power management settings.

 

 

Most of the internal state of the 82540EP is reset on the de-assertion (rising edge) of

 

 

RST#.

 

 

 

 

 

 

CLKRUN#

I/O

Clock Run. This signal is used by the system to pause

PCI clock signal. It is used

by the 82540EP controller to request the PCI clock. When the CLKRUN# feature is

OD

 

disabled, leave this pin unconnected.

 

 

 

 

 

 

 

 

 

3.2.5Error Reporting Signals

Symbol

Type

Name and Function

 

 

 

 

 

System Error. The System Error signal is used by the 82540EP controller to report

SERR#

OD

address parity errors. SERR# is open drain and

actively driven for a single PCI clock

 

 

when reporting the error.

 

 

 

 

 

 

Parity Error. The Parity Error signal is used by the 82540EP controller to report data

PERR#

STS

parity errors during all PCI transactions except by

Special Cycle. PERR# is sustained

tri-state and must be driven active by the 82540EP controller two data clocks after a

 

 

data parity error is detected. The minimum duration of PERR# is one clock for each

 

 

data phase a data parity error is present.

 

 

 

 

 

Datasheet

11

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Image 17
Intel 82540EP manual Arbitration Signals, Interrupt Signal, System Signals, Error Reporting Signals