Arbitration Signals, Interrupt Signal | Intel 82540EP specification

Networking Silicon — 82540EP

3.2.2Arbitration Signals

	Symbol	Type	Name and Function

	REQ#	TS	Request Bus. The Request Bus signal is used to request control of the bus from the
	REQ#	TS	arbiter. This signal is point-to-point.
			arbiter. This signal is point-to-point.

	GNT#	I	Grant Bus. The Grant Bus signal notifies the 82540EP that bus access has been
	GNT#	I	granted. This is a point-to-point signal.
			granted. This is a point-to-point signal.

			Lock Bus. The Lock Bus signal is asserted by an initiator to require sole access to a
	LOCK#	I	target memory device during two or more separate transfers. The 82540EP device
			does not implement bus locking.

3.2.3Interrupt Signal

	Symbol	Type	Name and Function

	INTA#	TS	Interrupt A. Interrupt A is used to request an interrupt by port 1 of the 82540EP. It is an
	INTA#	TS	active low, level-triggered interrupt signal.
			active low, level-triggered interrupt signal.

3.2.4System Signals

	Symbol	Type		Name and Function

			PCI Clock.
	CLK	I	82540EPsignal	all

	M66EN	I	66 MHz Enable. M66EN indicates whether the systemthebus		enabled for 66MHz.

			PCI Reset. When the PCI Reset signal is asserted, PCI output signals, except
			Power Management Event	(PME#), are floated and all input signals are ignored.
	RST#	I	The PME# context is preserved, depending on power management settings.
			Most of the internal state of the 82540EP is reset on the de-assertion (rising edge) of
			RST#.

	CLKRUN#	I/O	Clock Run. This signal is used by the system to pause		PCI clock signal. It is used
		I/O	by the 82540EP controller to request the PCI clock. When the CLKRUN# feature is
		OD
		OD	disabled, leave this pin unconnected.
			disabled, leave this pin unconnected.

3.2.5Error Reporting Signals

Symbol	Type	Name and Function

		System Error. The System Error signal is used by the 82540EP controller to report
SERR#	OD	address parity errors. SERR# is open drain and	actively driven for a single PCI clock
		when reporting the error.

		Parity Error. The Parity Error signal is used by the 82540EP controller to report data
PERR#	STS	parity errors during all PCI transactions except by	Special Cycle. PERR# is sustained
PERR#	STS	tri-state and must be driven active by the 82540EP controller two data clocks after a
		data parity error is detected. The minimum duration of PERR# is one clock for each
		data phase a data parity error is present.

Datasheet

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Intel 82540EP manual Arbitration Signals, Interrupt Signal, System Signals, Error Reporting Signals

Contents

Revision April 82540EP Gigabit Ethernet Controller Datasheet Date Revision 82540EP Networking Silicon Contents 82540EP Networking Silicon Introduction TX MAC MdioRX MAC Acpi LED Product Code Document ScopeReference Documents 82540EP Networking Silicon MAC Specific Features PCI FeaturesFeatures Benefits Application flexibility for LAN on Motherboard HostOffloading PHY Specific Features A server management processor Manageability Features Technology Features Additional Device Features PCI Address, Data and Control Signals Signal Type DefinitionsSymbol Type Name and Function PCI Bus Interface FRAME# STS PARIRDY# STS TRDY# STS Interrupt Signal Arbitration SignalsSystem Signals Error Reporting Signals Power Management Signals Eeprom and Serial Flash Interface SignalsImpedance Compensation Signals SMB Signals Other Signals Miscellaneous SignalsLED Signals XTAL2 AnalogXTAL1 Power Supply Connections Test Interface SignalsDigital Supplies Analog Supplies Ground and No Connects Control SignalsGND CTRL15 Recommended Operating Conditions Absolute Maximum RatingsAbsolute Maximum Ratingsa Recommended Operating Conditions a Sheet 1 DC Characteristics DC SpecificationsPower Specifications D0a Recommended Operating Conditions a Sheet 2 Power Specifications Complete Subsystem Power Specifications D3coldPower Specifications Dr Uninitialized = V SS O CharacteristicsSymbol Parameter Condition Min Typ Max AC Characteristics Symbol Parameter a PCI 66 MHz PCI 33 MHz Units Min Max Timing Specifications PCI Bus InterfacePCI Bus Interface Clock Parameters Tcyc PCI Bus Interface Timing Parameters Symbol Parameter PCI 66MHz PCI 33 MHz Units Min Max PCI Bus Interface Timing Measurement Conditions Symbol Parameter PCI 66 MHz UnitVTH VTL Inch max Point 50 pF PinInch max Point 1kΩ 10 pF Rise and Fall Times Link Interface TimingEeprom Interface 82540EP Product Name Device IdentificationYyww Date Code Package Information Datasheet Thermal Characteristics Thermal SpecificationsSymbol Parameter Value at specified airflow m/s Units Thermal resistance, junction-to-ambient Pinout Information Impedance Compensation Signals Power Management SignalsSMB Signals Eeprom and Serial Flash Interface Signals Test Interface Signals PHY SignalsDigital Power Signals Analog Power Signals Signal Names in Pin Order Sheet 1 Grounds and No Connect SignalsSignal Name Pin Lanpwrgood Smbclk RST# SMBALRT# Signal Names in Pin Order Sheet 2M66EN REQ# CBE3# CLKRUN# Smbdata GND CLK VIO TRDY# Zpcomp Signal Names in Pin Order Sheet 3IRDY# FRAME# CBE2# GND PAR PERR# GNT# Signal Names in Pin Order Sheet 4STOP# INTA# DEVSEL# Zncomp CBE0# PCIAD5 GND PCIAD1 Clkview FLCE# Eesk Signal Names in Pin Order Sheet 5CBE1# PCIAD9 PCIAD7 PCIAD4 Signal Names in Pin Order Sheet 6PCIAD8 PCIAD6 PCIAD3 PCIAD2 Eecs GND Flso Eedi Vddo P12 C D E F G H J K L M N P Visual Pin Reference